mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
240 lines
4.3 KiB
ArmAsm
240 lines
4.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include "mx35pdk.h"
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#include <asm/arch/lowlevel_macro.S>
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/*
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* return soc version
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* 0x10: TO1
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* 0x20: TO2
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* 0x30: TO3
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*/
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.macro check_soc_version ret, tmp
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ldr \tmp, =IIM_BASE_ADDR
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ldr \ret, [\tmp, #IIM_SREV]
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cmp \ret, #0x00
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moveq \tmp, #ROMPATCH_REV
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ldreq \ret, [\tmp]
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moveq \ret, \ret, lsl #4
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addne \ret, \ret, #0x10
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.endm
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/* CPLD on CS5 setup */
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.macro init_debug_board
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ldr r0, =DBG_BASE_ADDR
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ldr r1, =DBG_CSCR_U_CONFIG
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str r1, [r0, #0x00]
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ldr r1, =DBG_CSCR_L_CONFIG
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str r1, [r0, #0x04]
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ldr r1, =DBG_CSCR_A_CONFIG
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str r1, [r0, #0x08]
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.endm
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/* clock setup */
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.macro init_clock
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ldr r0, =CCM_BASE_ADDR
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/* default CLKO to 1/32 of the ARM core*/
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ldr r1, [r0, #CLKCTL_COSR]
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bic r1, r1, #0x00000FF00
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bic r1, r1, #0x0000000FF
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mov r2, #0x00006C00
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add r2, r2, #0x67
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orr r1, r1, r2
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str r1, [r0, #CLKCTL_COSR]
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ldr r2, =CCM_CCMR_CONFIG
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str r2, [r0, #CLKCTL_CCMR]
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check_soc_version r1, r2
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cmp r1, #CHIP_REV_2_0
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ldrhs r3, =CCM_MPLL_532_HZ
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bhs 1f
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ldr r2, [r0, #CLKCTL_PDR0]
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tst r2, #CLKMODE_CONSUMER
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ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
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ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
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1:
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str r3, [r0, #CLKCTL_MPCTL]
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ldr r1, =CCM_PPLL_300_HZ
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str r1, [r0, #CLKCTL_PPCTL]
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ldr r1, =CCM_PDR0_CONFIG
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bic r1, r1, #0x800000
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str r1, [r0, #CLKCTL_PDR0]
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ldr r1, [r0, #CLKCTL_CGR0]
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orr r1, r1, #0x0C300000
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str r1, [r0, #CLKCTL_CGR0]
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ldr r1, [r0, #CLKCTL_CGR1]
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orr r1, r1, #0x00000C00
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orr r1, r1, #0x00000003
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str r1, [r0, #CLKCTL_CGR1]
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ldr r1, [r0, #CLKCTL_CGR2]
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orr r1, r1, #0x00C00000
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str r1, [r0, #CLKCTL_CGR2]
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.endm
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.macro setup_sdram
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ldr r0, =ESDCTL_BASE_ADDR
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mov r3, #0x2000
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str r3, [r0, #0x0]
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str r3, [r0, #0x8]
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/*ip(r12) has used to save lr register in upper calling*/
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mov fp, lr
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #CSD0_BASE_ADDR
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bl setup_sdram_bank
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #CSD1_BASE_ADDR
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bl setup_sdram_bank
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mov lr, fp
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1:
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ldr r3, =ESDCTL_DELAY_LINE5
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str r3, [r0, #0x30]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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core_init
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init_aips
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init_max
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init_m3if
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init_clock
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init_debug_board
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cmp pc, #PHYS_SDRAM_1
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blo init_sdram_start
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cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
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blo skip_sdram_setup
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init_sdram_start:
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/*init_sdram*/
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setup_sdram
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skip_sdram_setup:
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mov lr, r10
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mov pc, lr
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/*
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* r0: ESDCTL control base, r1: sdram slot base
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* r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
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*/
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setup_sdram_bank:
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mov r3, #0xE
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tst r2, #0x1
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orreq r3, r3, #0x300 /*DDR2*/
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str r3, [r0, #0x10]
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bic r3, r3, #0x00A
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str r3, [r0, #0x10]
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beq 2f
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mov r3, #0x20000
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1: subs r3, r3, #1
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bne 1b
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2: tst r2, #0x1
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ldreq r3, =ESDCTL_DDR2_CONFIG
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ldrne r3, =ESDCTL_MDDR_CONFIG
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cmp r1, #CSD1_BASE_ADDR
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strlo r3, [r0, #0x4]
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strhs r3, [r0, #0xC]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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tst r2, #0x1
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bne skip_set_mode
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_DDR2_EMR2
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EMR3
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EN_DLL
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_RESET_DLL
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strb r3, [r1, r4]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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skip_set_mode:
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xA2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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strb r3, [r1]
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strb r3, [r1]
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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ldreq r4, =ESDCTL_DDR2_MR
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ldrne r4, =ESDCTL_MDDR_MR
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mov r3, #0xDA
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strb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
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streqb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_EN_DLL
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ldrne r4, =ESDCTL_MDDR_EMR
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strb r3, [r1, r4]
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0x82228080
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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moveq r4, #0x20000
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movne r4, #0x200
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1: subs r4, r4, #1
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bne 1b
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str r3, [r1, #0x100]
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ldr r4, [r1, #0x100]
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cmp r3, r4
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movne r3, #1
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moveq r3, #0
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mov pc, lr
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