mirror of
https://github.com/brain-hackers/u-boot-brain
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9d6c9d988f
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* Sunxi ehci glue
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/usb_phy.h>
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#include <asm/io.h>
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#include <dm.h>
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#include "ehci.h"
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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#define BASE_DIST 0x8000
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#define AHB_CLK_DIST 2
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#else
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#define BASE_DIST 0x1000
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#define AHB_CLK_DIST 1
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#endif
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struct ehci_sunxi_priv {
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struct ehci_ctrl ehci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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int phy_index; /* Index of the usb-phy attached to this hcd */
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};
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct usb_platdata *plat = dev_get_platdata(dev);
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struct ehci_sunxi_priv *priv = dev_get_priv(dev);
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struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
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struct ehci_hcor *hcor;
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int extra_ahb_gate_mask = 0;
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/*
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* This should go away once we've moved to the driver model for
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* clocks resp. phys.
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*/
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priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
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#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
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extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
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#endif
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priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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priv->phy_index++; /* Non otg phys start at 1 */
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setbits_le32(&ccm->ahb_gate0,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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setbits_le32(&ccm->ahb_reset0_cfg,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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#endif
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sunxi_usb_phy_init(priv->phy_index);
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sunxi_usb_phy_power_on(priv->phy_index);
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hcor = (struct ehci_hcor *)((uintptr_t)hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
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}
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static int ehci_usb_remove(struct udevice *dev)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct ehci_sunxi_priv *priv = dev_get_priv(dev);
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int ret;
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ret = ehci_deregister(dev);
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if (ret)
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return ret;
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sunxi_usb_phy_exit(priv->phy_index);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
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#endif
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clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
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return 0;
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}
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-ehci", },
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{ .compatible = "allwinner,sun5i-a13-ehci", },
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{ .compatible = "allwinner,sun6i-a31-ehci", },
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{ .compatible = "allwinner,sun7i-a20-ehci", },
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{ .compatible = "allwinner,sun8i-a23-ehci", },
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{ .compatible = "allwinner,sun8i-a83t-ehci", },
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{ .compatible = "allwinner,sun8i-h3-ehci", },
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{ .compatible = "allwinner,sun9i-a80-ehci", },
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{ .compatible = "allwinner,sun50i-a64-ehci", },
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{ }
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};
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U_BOOT_DRIVER(ehci_sunxi) = {
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.name = "ehci_sunxi",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.probe = ehci_usb_probe,
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.remove = ehci_usb_remove,
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.ops = &ehci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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