mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 10:28:51 +09:00
e7dcf5645f
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
295 lines
7.2 KiB
C
295 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for IGEP COM AQUILA and SMARC AM335x based boards
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*
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* Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <fdt_support.h>
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#include <mtd_node.h>
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#include <jffs2/load_kernel.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
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* and control IGEP0034 green and red LEDs.
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* U-boot configures these pins as input pullup to detect board revision:
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* IGEP0034-LITE = 0b00
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* IGEP0034 (FULL) = 0b01
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* IGEP0033 = 0b1X
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*/
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#define GPIO_GREEN_REVISION 27
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#define GPIO_RED_REVISION 26
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/*
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* Routine: get_board_revision
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* Description: Returns the board revision
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*/
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static int get_board_revision(void)
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{
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int revision;
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gpio_request(GPIO_GREEN_REVISION, "green_revision");
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gpio_direction_input(GPIO_GREEN_REVISION);
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revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
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gpio_free(GPIO_GREEN_REVISION);
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gpio_request(GPIO_RED_REVISION, "red_revision");
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gpio_direction_input(GPIO_RED_REVISION);
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revision = revision + gpio_get_value(GPIO_RED_REVISION);
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gpio_free(GPIO_RED_REVISION);
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return revision;
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}
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#ifdef CONFIG_SPL_BUILD
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/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
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static const struct ddr_data ddr3_igep0034_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct ddr_data ddr3_igep0034_lite_data = {
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.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
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.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
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.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
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.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
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.cmd0csratio = K4B2G1646EBIH9_RATIO,
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.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd1csratio = K4B2G1646EBIH9_RATIO,
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.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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.cmd2csratio = K4B2G1646EBIH9_RATIO,
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.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_igep0034_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
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.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
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.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
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.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
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.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
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.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
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.zq_config = K4B2G1646EBIH9_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
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};
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const struct ctrl_ioregs ioregs_igep0034 = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs_igep0034_lite = {
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.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
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.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
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.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
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.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
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.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
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};
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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400, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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void sdram_init(void)
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{
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if (get_board_revision() == 1)
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config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
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&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
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else
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config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
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&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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switch (get_board_revision()) {
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case 0:
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env_set("board_name", "igep0034-lite");
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break;
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case 1:
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env_set("board_name", "igep0034");
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break;
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default:
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env_set("board_name", "igep0033");
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break;
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}
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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static const struct node_info nodes[] = {
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{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
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};
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_DRIVER_TI_CPSW)
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, ret = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
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&cdev->miisel);
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if (get_board_revision() == 1)
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cpsw_slaves[0].phy_addr = 1;
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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ret += rv;
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return ret;
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}
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#endif
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