mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
bba22a97a7
The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
45 lines
1.0 KiB
Plaintext
45 lines
1.0 KiB
Plaintext
CONFIG_X86=y
|
|
CONFIG_SYS_MALLOC_F_LEN=0x1800
|
|
CONFIG_VENDOR_GOOGLE=y
|
|
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
|
|
CONFIG_TARGET_CHROMEBOOK_LINK=y
|
|
CONFIG_HAVE_MRC=y
|
|
CONFIG_ENABLE_MRC_CACHE=y
|
|
CONFIG_SMP=y
|
|
CONFIG_HAVE_VGA_BIOS=y
|
|
CONFIG_CMD_CPU=y
|
|
# CONFIG_CMD_IMLS is not set
|
|
# CONFIG_CMD_FLASH is not set
|
|
CONFIG_CMD_GPIO=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
# CONFIG_CMD_NFS is not set
|
|
CONFIG_BOOTSTAGE=y
|
|
CONFIG_BOOTSTAGE_REPORT=y
|
|
CONFIG_CMD_BOOTSTAGE=y
|
|
CONFIG_CMD_TPM=y
|
|
CONFIG_CMD_TPM_TEST=y
|
|
CONFIG_OF_CONTROL=y
|
|
CONFIG_CPU=y
|
|
CONFIG_CMD_CROS_EC=y
|
|
CONFIG_CROS_EC=y
|
|
CONFIG_CROS_EC_LPC=y
|
|
CONFIG_SPI_FLASH=y
|
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
CONFIG_SPI_FLASH_MACRONIX=y
|
|
CONFIG_SPI_FLASH_WINBOND=y
|
|
CONFIG_DM_PCI=y
|
|
CONFIG_DM_RTC=y
|
|
CONFIG_DEBUG_UART=y
|
|
CONFIG_DEBUG_UART_BASE=0x3f8
|
|
CONFIG_DEBUG_UART_CLOCK=1843200
|
|
CONFIG_DEBUG_UART_BOARD_INIT=y
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_ICH_SPI=y
|
|
CONFIG_TIMER=y
|
|
CONFIG_TPM_TIS_LPC=y
|
|
CONFIG_VIDEO_VESA=y
|
|
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
|
|
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
|
|
CONFIG_USE_PRIVATE_LIBGCC=y
|
|
CONFIG_TPM=y
|