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https://github.com/brain-hackers/u-boot-brain
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6f9cc6608b
The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
22 lines
589 B
C
22 lines
589 B
C
#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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#define FSL_SERDES_CLK_100 (0 << 28)
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#define FSL_SERDES_CLK_125 (1 << 28)
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#define FSL_SERDES_CLK_150 (3 << 28)
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#define FSL_SERDES_PROTO_SATA 0
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#define FSL_SERDES_PROTO_PEX 1
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#define FSL_SERDES_PROTO_PEX_X2 2
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#define FSL_SERDES_PROTO_SGMII 3
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#define FSL_SERDES_VDD_1V 1
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#ifdef CONFIG_FSL_SERDES
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extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
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#else
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static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
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#endif /* CONFIG_FSL_SERDES */
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#endif /* __FSL_SERDES_H */
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