mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-04 01:03:45 +09:00
86b657878b
For Tegra20, the SKU ID actually impacts how U-Boot programs the chip, and hence we need to explicitly know about each and every SKU ID in order to operate correctly. However, for Tegra30/114, this isn't the case. Rather than forcing each new user with a different SKU to manually add their SKU ID into the code, simply accept any SKU ID. If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll need to undo this, or make the default case map to conservative defaults, but for now it's likely the path to least support cost. Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
159 lines
3.4 KiB
C
159 lines
3.4 KiB
C
/*
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* (C) Copyright 2010-2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra AP (Application Processor) code */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/clock.h>
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#include <asm/arch-tegra/fuse.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/scu.h>
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#include <asm/arch-tegra/tegra.h>
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#include <asm/arch-tegra/warmboot.h>
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int tegra_get_chip(void)
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{
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int rev;
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struct apb_misc_gp_ctlr *gp =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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/*
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* This is undocumented, Chip ID is bits 15:8 of the register
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* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
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* Tegra30, and 0x35 for T114.
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*/
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rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
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debug("%s: CHIPID is 0x%02X\n", __func__, rev);
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return rev;
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}
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int tegra_get_sku_info(void)
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{
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int sku_id;
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struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
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sku_id = readl(&fuse->sku_info) & 0xff;
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debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
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return sku_id;
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}
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int tegra_get_chip_sku(void)
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{
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uint sku_id, chip_id;
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chip_id = tegra_get_chip();
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sku_id = tegra_get_sku_info();
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switch (chip_id) {
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case CHIPID_TEGRA20:
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switch (sku_id) {
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case SKU_ID_T20_7:
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case SKU_ID_T20:
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return TEGRA_SOC_T20;
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case SKU_ID_T25SE:
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case SKU_ID_AP25:
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case SKU_ID_T25:
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case SKU_ID_AP25E:
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case SKU_ID_T25E:
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return TEGRA_SOC_T25;
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}
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break;
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case CHIPID_TEGRA30:
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switch (sku_id) {
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case SKU_ID_T33:
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case SKU_ID_T30:
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case SKU_ID_TM30MQS_P_A3:
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default:
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return TEGRA_SOC_T30;
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}
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break;
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case CHIPID_TEGRA114:
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switch (sku_id) {
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case SKU_ID_T114_ENG:
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case SKU_ID_T114_1:
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default:
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return TEGRA_SOC_T114;
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}
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break;
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}
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/* unknown chip/sku id */
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printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
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__func__, chip_id, sku_id);
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return TEGRA_SOC_UNKNOWN;
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}
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static void enable_scu(void)
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{
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struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
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u32 reg;
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/* Only enable the SCU on T20/T25 */
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if (tegra_get_chip() != CHIPID_TEGRA20)
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return;
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/* If SCU already setup/enabled, return */
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if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
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return;
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/* Invalidate all ways for all processors */
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writel(0xFFFF, &scu->scu_inv_all);
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/* Enable SCU - bit 0 */
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reg = readl(&scu->scu_ctrl);
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reg |= SCU_CTRL_ENABLE;
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writel(reg, &scu->scu_ctrl);
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}
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static u32 get_odmdata(void)
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{
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/*
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* ODMDATA is stored in the BCT in IRAM by the BootROM.
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* The BCT start and size are stored in the BIT in IRAM.
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* Read the data @ bct_start + (bct_size - 12). This works
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* on T20 and T30 BCTs, which are locked down. If this changes
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* in new chips (T114, etc.), we can revisit this algorithm.
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*/
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u32 bct_start, odmdata;
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bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
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odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
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return odmdata;
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}
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static void init_pmc_scratch(void)
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{
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 odmdata;
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int i;
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/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
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for (i = 0; i < 23; i++)
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writel(0, &pmc->pmc_scratch1+i);
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/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
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odmdata = get_odmdata();
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writel(odmdata, &pmc->pmc_scratch20);
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}
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void s_init(void)
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{
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/* Init PMC scratch memory */
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init_pmc_scratch();
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enable_scu();
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/* init the cache */
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config_cache();
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}
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