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https://github.com/brain-hackers/u-boot-brain
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9ca5a0ca0e
The name of coreboot.dtsi is misleading, as it actually describes the legacy serial port device node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
61 lines
937 B
Plaintext
61 lines
937 B
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/include/ "serial.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Intel Crown Bay";
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compatible = "intel,crownbay", "intel,queensbay";
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config {
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silent_console = <0>;
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich7";
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spi-flash@0 {
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reg = <0>;
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compatible = "sst,25vf016b", "spi-flash";
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memory-map = <0xffe00000 0x00200000>;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m0220661105_cv.dtsi"
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};
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};
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};
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