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https://github.com/brain-hackers/u-boot-brain
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9c7dea602e
PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
10 lines
175 B
Makefile
10 lines
175 B
Makefile
#
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# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += fsp_configs.o
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obj-y += tnc.o topcliff.o
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obj-$(CONFIG_PCI) += tnc_pci.o
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