Matthew McClintock 9c6b47d53e p1014rdb: set ddr bus width properly depending on SVR ... Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-08-23 10:24:16 -05:00
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cpu	powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list	2012-08-23 10:24:16 -05:00
include/asm	p1014rdb: set ddr bus width properly depending on SVR	2012-08-23 10:24:16 -05:00
lib	powerpc: Stack Pointer not properly aligned	2012-08-22 16:07:42 -05:00
config.mk	Handle most LDSCRIPT setting centrally	2011-04-30 00:59:47 +02:00