mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 03:19:43 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) STMicroelectronics SA 2017
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* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
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*/
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#ifndef __STM32_RCC_H_
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#define __STM32_RCC_H_
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#define AHB_PSC_1 0
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#define AHB_PSC_2 0x8
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#define AHB_PSC_4 0x9
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#define AHB_PSC_8 0xA
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#define AHB_PSC_16 0xB
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#define AHB_PSC_64 0xC
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#define AHB_PSC_128 0xD
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#define AHB_PSC_256 0xE
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#define AHB_PSC_512 0xF
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#define APB_PSC_1 0
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#define APB_PSC_2 0x4
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#define APB_PSC_4 0x5
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#define APB_PSC_8 0x6
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#define APB_PSC_16 0x7
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struct pll_psc {
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u8 pll_m;
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u16 pll_n;
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u8 pll_p;
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u8 pll_q;
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u8 ahb_psc;
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u8 apb1_psc;
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u8 apb2_psc;
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};
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struct stm32_clk_info {
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struct pll_psc sys_pll_psc;
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bool has_overdrive;
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bool v2;
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};
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enum soc_family {
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STM32F4,
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STM32F7,
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};
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enum apb {
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APB1,
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APB2,
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};
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struct stm32_rcc_clk {
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char *drv_name;
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enum soc_family soc;
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};
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struct stm32_rcc_regs {
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u32 cr; /* RCC clock control */
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u32 pllcfgr; /* RCC PLL configuration */
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u32 cfgr; /* RCC clock configuration */
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u32 cir; /* RCC clock interrupt */
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u32 ahb1rstr; /* RCC AHB1 peripheral reset */
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u32 ahb2rstr; /* RCC AHB2 peripheral reset */
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u32 ahb3rstr; /* RCC AHB3 peripheral reset */
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u32 rsv0;
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u32 apb1rstr; /* RCC APB1 peripheral reset */
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u32 apb2rstr; /* RCC APB2 peripheral reset */
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u32 rsv1[2];
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u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
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u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
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u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
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u32 rsv2;
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u32 apb1enr; /* RCC APB1 peripheral clock enable */
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u32 apb2enr; /* RCC APB2 peripheral clock enable */
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u32 rsv3[2];
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u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
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u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
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u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
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u32 rsv4;
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u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
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u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
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u32 rsv5[2];
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u32 bdcr; /* RCC Backup domain control */
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u32 csr; /* RCC clock control & status */
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u32 rsv6[2];
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u32 sscgr; /* RCC spread spectrum clock generation */
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u32 plli2scfgr; /* RCC PLLI2S configuration */
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/* below registers are only available on STM32F46x and STM32F7 SoCs*/
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u32 pllsaicfgr; /* PLLSAI configuration */
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u32 dckcfgr; /* dedicated clocks configuration register */
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/* Below registers are only available on STM32F7 SoCs */
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u32 dckcfgr2; /* dedicated clocks configuration register */
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};
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#endif /* __STM32_RCC_H_ */
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