mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-03 10:00:42 +09:00
9c66ce662c
This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
||
|---|---|---|
| .. | ||
| cpu.c | ||
| cpu.h | ||
| fdt.c | ||
| lowlevel.S | ||
| Makefile | ||
| mp.c | ||
| mp.h | ||
| README | ||
| speed.c | ||
| speed.h | ||
# # Copyright 2014 Freescale Semiconductor # # SPDX-License-Identifier: GPL-2.0+ # Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A.