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5699274373
Defining variable gic_dist_addr as a globe one prevents some functions, which use it, from being used before relocation which is the case in the deep sleep resume process on Freescale SoC platforms. Besides, we can always get the GIC base address by calling get_gicd_base_address() without referring gic_dist_addr. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
/*
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* (C) Copyright 2013
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* Andre Przywara, Linaro <andre.przywara@linaro.org>
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*
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* Routines to transition ARMv7 processors from secure into non-secure state
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* and from non-secure SVC into HYP mode
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* needed to enable ARMv7 virtualization for current hypervisors
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/secure.h>
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static unsigned int read_id_pfr1(void)
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{
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unsigned int reg;
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asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
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return reg;
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}
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static unsigned long get_gicd_base_address(void)
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{
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#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
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return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
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#else
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unsigned periphbase;
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/* get the GIC base address from the CBAR register */
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asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
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/* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
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* encode this). Bail out here since we cannot access this without
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* enabling paging.
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*/
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if ((periphbase & 0xff) != 0) {
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printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
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return -1;
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}
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return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
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#endif
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}
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static void relocate_secure_section(void)
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{
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#ifdef CONFIG_ARMV7_SECURE_BASE
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size_t sz = __secure_end - __secure_start;
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memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
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flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
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CONFIG_ARMV7_SECURE_BASE + sz + 1);
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invalidate_icache_all();
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#endif
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}
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static void kick_secondary_cpus_gic(unsigned long gicdaddr)
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{
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/* kick all CPUs (except this one) by writing to GICD_SGIR */
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writel(1U << 24, gicdaddr + GICD_SGIR);
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}
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void __weak smp_kick_all_cpus(void)
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{
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unsigned long gic_dist_addr;
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gic_dist_addr = get_gicd_base_address();
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if (gic_dist_addr == -1)
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return;
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kick_secondary_cpus_gic(gic_dist_addr);
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}
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int armv7_init_nonsec(void)
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{
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unsigned int reg;
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unsigned itlinesnr, i;
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unsigned long gic_dist_addr;
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/* check whether the CPU supports the security extensions */
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reg = read_id_pfr1();
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if ((reg & 0xF0) == 0) {
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printf("nonsec: Security extensions not implemented.\n");
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return -1;
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}
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/* the SCR register will be set directly in the monitor mode handler,
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* according to the spec one should not tinker with it in secure state
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* in SVC mode. Do not try to read it once in non-secure state,
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* any access to it will trap.
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*/
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gic_dist_addr = get_gicd_base_address();
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if (gic_dist_addr == -1)
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return -1;
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/* enable the GIC distributor */
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writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
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gic_dist_addr + GICD_CTLR);
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/* TYPER[4:0] contains an encoded number of available interrupts */
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itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
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/* set all bits in the GIC group registers to one to allow access
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* from non-secure state. The first 32 interrupts are private per
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* CPU and will be set later when enabling the GIC for each core
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*/
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for (i = 1; i <= itlinesnr; i++)
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writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
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#ifndef CONFIG_ARMV7_PSCI
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smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
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smp_kick_all_cpus();
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#endif
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/* call the non-sec switching code on this CPU also */
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relocate_secure_section();
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secure_ram_addr(_nonsec_init)();
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return 0;
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}
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