mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#include <asm/mmu.h>
|
|
#include <asm/io.h>
|
|
#include <common.h>
|
|
#include <mpc83xx.h>
|
|
#include <pci.h>
|
|
#include <i2c.h>
|
|
#include <fdt_support.h>
|
|
#include <asm/fsl_i2c.h>
|
|
#include <asm/fsl_mpc83xx_serdes.h>
|
|
|
|
static struct pci_region pci_regions[] = {
|
|
{
|
|
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
|
phys_start: CONFIG_SYS_PCI_MEM_PHYS,
|
|
size: CONFIG_SYS_PCI_MEM_SIZE,
|
|
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
|
},
|
|
{
|
|
bus_start: CONFIG_SYS_PCI_MMIO_BASE,
|
|
phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
|
|
size: CONFIG_SYS_PCI_MMIO_SIZE,
|
|
flags: PCI_REGION_MEM
|
|
},
|
|
{
|
|
bus_start: CONFIG_SYS_PCI_IO_BASE,
|
|
phys_start: CONFIG_SYS_PCI_IO_PHYS,
|
|
size: CONFIG_SYS_PCI_IO_SIZE,
|
|
flags: PCI_REGION_IO
|
|
}
|
|
};
|
|
|
|
static struct pci_region pcie_regions_0[] = {
|
|
{
|
|
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
|
|
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
|
|
.flags = PCI_REGION_MEM,
|
|
},
|
|
{
|
|
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
|
|
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
|
|
.size = CONFIG_SYS_PCIE1_IO_SIZE,
|
|
.flags = PCI_REGION_IO,
|
|
},
|
|
};
|
|
|
|
static struct pci_region pcie_regions_1[] = {
|
|
{
|
|
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
|
|
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
|
|
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
|
|
.flags = PCI_REGION_MEM,
|
|
},
|
|
{
|
|
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
|
|
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
|
|
.size = CONFIG_SYS_PCIE2_IO_SIZE,
|
|
.flags = PCI_REGION_IO,
|
|
},
|
|
};
|
|
|
|
static int is_pex_x2(void)
|
|
{
|
|
const char *pex_x2 = env_get("pex_x2");
|
|
|
|
if (pex_x2 && !strcmp(pex_x2, "yes"))
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
|
volatile sysconf83xx_t *sysconf = &immr->sysconf;
|
|
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
|
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
|
volatile law83xx_t *pcie_law = sysconf->pcielaw;
|
|
struct pci_region *reg[] = { pci_regions };
|
|
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
|
|
u32 spridr = in_be32(&immr->sysconf.spridr);
|
|
int pex2 = is_pex_x2();
|
|
|
|
if (board_pci_host_broken())
|
|
goto skip_pci;
|
|
|
|
/* Enable all 5 PCI_CLK_OUTPUTS */
|
|
clk->occr |= 0xf8000000;
|
|
udelay(2000);
|
|
|
|
/* Configure PCI Local Access Windows */
|
|
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
|
|
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
|
|
|
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
|
|
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
|
|
|
udelay(2000);
|
|
|
|
mpc83xx_pci_init(1, reg);
|
|
skip_pci:
|
|
/* There is no PEX in MPC8379 parts. */
|
|
if (PARTID_NO_E(spridr) == SPR_8379)
|
|
return;
|
|
|
|
if (pex2)
|
|
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
|
|
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
|
|
else
|
|
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
|
|
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
|
|
|
|
/* Configure the clock for PCIE controller */
|
|
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
|
|
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
|
|
|
|
/* Deassert the resets in the control register */
|
|
out_be32(&sysconf->pecr1, 0xE0008000);
|
|
if (!pex2)
|
|
out_be32(&sysconf->pecr2, 0xE0008000);
|
|
udelay(2000);
|
|
|
|
/* Configure PCI Express Local Access Windows */
|
|
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
|
|
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
|
|
|
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
|
|
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
|
|
|
mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
|
|
}
|
|
|
|
void ft_pcie_fixup(void *blob, bd_t *bd)
|
|
{
|
|
const char *status = "disabled (PCIE1 is x2)";
|
|
|
|
if (!is_pex_x2())
|
|
return;
|
|
|
|
do_fixup_by_path(blob, "pci2", "status", status,
|
|
strlen(status) + 1, 1);
|
|
}
|