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brain-hackers_pepepper-mirror
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u-boot-brain
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9c486e7cb0
u-boot-brain
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drivers
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ddr
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Tom Rini
d61639e39a
Merge git://git.denx.de/u-boot-socfpga
2018-01-27 14:48:41 -05:00
..
altera
ddr: altera: silence PHY calibration unless in debug mode
2018-01-25 09:59:37 +01:00
fsl
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
2018-01-23 11:20:03 -08:00
marvell
ddr: marvell: update ddr controller init and freq
2018-01-19 16:30:29 +01:00
microchip
wait_bit: use wait_for_bit_le32 and remove wait_for_bit
2018-01-24 12:03:43 +05:30
Kconfig
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig
2017-04-14 14:06:57 +02:00