mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-09 06:13:21 +09:00
789edf694c
Convert the R8A7791 Porter board to DM and DT. This implies mostly enabling the necessary configuration options and plucking out the ad-hoc configuration from the board file. Moreover, the pre-reloc malloc size was increased to allow the clock driver to start up early without running out of malloc space and the early stack was moved further up in the DRAM to avoid rewriting U-Boot itself. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
/*
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* board/renesas/porter/porter.c
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <div64.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.5GHz */
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stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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/* QoS */
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qos_init();
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}
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#define TMU0_MSTP125 BIT(25)
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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int board_early_init_f(void)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD2CKCR);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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/* porter has KSZ8041RNLI */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC0000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_ARCH_RMOBILE_BOARD_STRING
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};
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void reset_cpu(ulong addr)
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{
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u8 val;
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i2c_set_bus_num(2); /* PowerIC connected to ch2 */
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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