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https://github.com/brain-hackers/u-boot-brain
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f80e61dcfe
Here you find all the changes in the include directory for new register names and adapting other ones to the names used by AMCC in their manuals, e.g. For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008 For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006 Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
124 lines
4.1 KiB
C
124 lines
4.1 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _4xx_i2c_h_
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#define _4xx_i2c_h_
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#define IIC_OK 0
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#define IIC_NOK 1
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#define IIC_NOK_LA 2 /* Lost arbitration */
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#define IIC_NOK_ICT 3 /* Incomplete transfer */
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#define IIC_NOK_XFRA 4 /* Transfer aborted */
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#define IIC_NOK_DATA 5 /* No data in buffer */
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#define IIC_NOK_TOUT 6 /* Transfer timeout */
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#define IIC_TIMEOUT 1 /* 1 second */
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#if defined(CONFIG_I2C_MULTI_BUS)
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#define I2C_BUS_OFFS (i2c_bus_num * 0x100)
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#else
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#define I2C_BUS_OFFS (0x000)
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#endif /* CONFIG_I2C_MULTI_BUS */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
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#elif defined(CONFIG_440) || defined(CONFIG_405EX)
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/* all remaining 440 variants */
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#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
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#else
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/* all 405 variants */
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#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
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#endif
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#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
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#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
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#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
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#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
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#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
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#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
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#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
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#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
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#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
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#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
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#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
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#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
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#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
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#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
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#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
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#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
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/* MDCNTL Register Bit definition */
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#define IIC_MDCNTL_HSCL 0x01
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#define IIC_MDCNTL_EUBS 0x02
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#define IIC_MDCNTL_EINT 0x04
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#define IIC_MDCNTL_ESM 0x08
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#define IIC_MDCNTL_FSM 0x10
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#define IIC_MDCNTL_EGC 0x20
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#define IIC_MDCNTL_FMDB 0x40
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#define IIC_MDCNTL_FSDB 0x80
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/* CNTL Register Bit definition */
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#define IIC_CNTL_PT 0x01
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#define IIC_CNTL_READ 0x02
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#define IIC_CNTL_CHT 0x04
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#define IIC_CNTL_RPST 0x08
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/* bit 2/3 for Transfer count*/
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#define IIC_CNTL_AMD 0x40
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#define IIC_CNTL_HMT 0x80
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/* STS Register Bit definition */
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#define IIC_STS_PT 0x01
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#define IIC_STS_IRQA 0x02
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#define IIC_STS_ERR 0x04
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#define IIC_STS_SCMP 0x08
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#define IIC_STS_MDBF 0x10
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#define IIC_STS_MDBS 0x20
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#define IIC_STS_SLPR 0x40
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#define IIC_STS_SSS 0x80
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/* EXTSTS Register Bit definition */
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#define IIC_EXTSTS_XFRA 0x01
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#define IIC_EXTSTS_ICT 0x02
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#define IIC_EXTSTS_LA 0x04
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/* XTCNTLSS Register Bit definition */
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#define IIC_XTCNTLSS_SRST 0x01
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#define IIC_XTCNTLSS_EPI 0x02
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#define IIC_XTCNTLSS_SDBF 0x04
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#define IIC_XTCNTLSS_SBDD 0x08
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#define IIC_XTCNTLSS_SWS 0x10
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#define IIC_XTCNTLSS_SWC 0x20
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#define IIC_XTCNTLSS_SRS 0x40
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#define IIC_XTCNTLSS_SRC 0x80
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/* IICx_DIRECTCNTL register */
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#define IIC_DIRCNTL_SDAC 0x08
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#define IIC_DIRCNTL_SCC 0x04
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#define IIC_DIRCNTL_MSDA 0x02
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#define IIC_DIRCNTL_MSC 0x01
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#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
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#endif
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