mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 23:03:45 +09:00
d40d69ee35
ARM CPUs can architecturally (speculatively) prefetch completely arbitrary normal memory locations, as defined by the current translation tables. The current MMU configuration for 64-bit Tegras maps an extremely large range of addresses as DRAM, well beyond the actual physical maximum DRAM window, even though U-Boot only needs access to the first 2GB of DRAM; the Tegra port of U-Boot deliberately limits itself to 2GB of RAM since some HW modules on at least some 64-bit Tegra SoCs can only access a 32-bit physical address space. This change reduces the amount of RAM mapped via the MMU to disallow the CPU from ever speculatively accessing RAM that U-Boot will definitely not access. This avoids the possibility of the HW raising SError due to accesses to always-invalid physical addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
||
---|---|---|
.. | ||
tegra20 | ||
tegra30 | ||
tegra114 | ||
tegra124 | ||
tegra186 | ||
tegra210 | ||
ap.c | ||
arm64-mmu.c | ||
board2.c | ||
board186.c | ||
board.c | ||
cache.c | ||
clock.c | ||
cmd_enterrcm.c | ||
cpu.c | ||
cpu.h | ||
dt-setup.c | ||
emc.c | ||
emc.h | ||
gpu.c | ||
ivc.c | ||
Kconfig | ||
lowlevel_init.S | ||
Makefile | ||
pinmux-common.c | ||
powergate.c | ||
psci.S | ||
spl.c | ||
sys_info.c | ||
xusb-padctl-common.c | ||
xusb-padctl-common.h | ||
xusb-padctl-dummy.c |