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https://github.com/brain-hackers/u-boot-brain
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e7a0de2c31
As the Ocelot and Luton SoCs, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
26 lines
979 B
C
26 lines
979 B
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
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#define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
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#define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
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#define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
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#define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))
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#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
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#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
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#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
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#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
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#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
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#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
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#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
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#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
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#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
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#endif
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