mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 02:49:44 +09:00
30088b0997
Move headers to mach-socfpga as well. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _RESET_MANAGER_H_
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#define _RESET_MANAGER_H_
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void reset_cpu(ulong addr);
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void reset_deassert_peripherals_handoff(void);
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void socfpga_bridges_reset(int enable);
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void socfpga_emac_reset(int enable);
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void socfpga_watchdog_reset(void);
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void socfpga_spim_enable(void);
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void socfpga_uart0_enable(void);
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void socfpga_sdram_enable(void);
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void socfpga_osc1timer_enable(void);
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struct socfpga_reset_manager {
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u32 status;
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u32 ctrl;
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u32 counts;
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u32 padding1;
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u32 mpu_mod_reset;
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u32 per_mod_reset;
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u32 per2_mod_reset;
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u32 brg_mod_reset;
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};
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
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#else
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
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#endif
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#define RSTMGR_PERMODRST_EMAC0_LSB 0
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#define RSTMGR_PERMODRST_EMAC1_LSB 1
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#define RSTMGR_PERMODRST_L4WD0_LSB 6
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#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8
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#define RSTMGR_PERMODRST_UART0_LSB 16
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#define RSTMGR_PERMODRST_SPIM0_LSB 18
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#define RSTMGR_PERMODRST_SPIM1_LSB 19
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#define RSTMGR_PERMODRST_SDR_LSB 29
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#endif /* _RESET_MANAGER_H_ */
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