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d04a46426b
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
14 lines
250 B
C
14 lines
250 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2020 SiFive, Inc.
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*
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* Author: Sagar Kadam <sagar.kadam@sifive.com>
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*/
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#ifndef __RESET_SIFIVE_H
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#define __RESET_SIFIVE_H
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int sifive_reset_bind(struct udevice *dev, ulong count);
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#endif
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