u-boot-brain/arch/riscv/include/asm/arch-fu540/cache.h
Pragnesh Patel 5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03 15:09:06 +08:00

15 lines
253 B
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifve.com>
*/
#ifndef _CACHE_SIFIVE_H
#define _CACHE_SIFIVE_H
int cache_enable_ways(void);
#endif /* _CACHE_SIFIVE_H */