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856e4b0d7f
When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ddr | ||
cpu.c | ||
fdt.c | ||
fsl_lbc.c | ||
Makefile | ||
srio.c |