mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
![Wolfgang Denk](/assets/img/avatar_default.png)
* 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
434 lines
12 KiB
C
434 lines
12 KiB
C
/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <pmic.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 system_rev;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR, 1},
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{MMC_SDHC2_BASE_ADDR, 1},
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};
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#endif
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u32 get_board_rev(void)
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{
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return system_rev;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
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mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
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mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
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/*FEC_MDC*/
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mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
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/* FEC RDATA[3] */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
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/* FEC RDATA[2] */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
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/* FEC RDATA[1] */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
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/* FEC RDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
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/* FEC TDATA[3] */
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mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
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/* FEC TDATA[2] */
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mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
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/* FEC TDATA[1] */
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mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
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/* FEC TDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
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/* FEC TX_EN */
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mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
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/* FEC TX_ER */
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mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
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/* FEC TX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
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/* FEC TX_COL */
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mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
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/* FEC RX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
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/* FEC RX_CRS */
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mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
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/* FEC RX_ER */
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mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
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/* FEC RX_DV */
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mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
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}
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#ifdef CONFIG_MXC_SPI
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static void setup_iomux_spi(void)
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{
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/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
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/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
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/* de-select SS1 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
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/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
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/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
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/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
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}
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#endif
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static void power_init(void)
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{
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unsigned int val;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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struct pmic *p;
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pmic_init();
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p = get_pmic();
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/* Write needed to Power Gate 2 register */
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pmic_reg_read(p, REG_POWER_MISC, &val);
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val &= ~PWGT2SPIEN;
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pmic_reg_write(p, REG_POWER_MISC, val);
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/* Externally powered */
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pmic_reg_read(p, REG_CHARGE, &val);
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val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
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pmic_reg_write(p, REG_CHARGE, val);
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/* power up the system first */
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pmic_reg_write(p, REG_POWER_MISC, PWUP);
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/* Set core voltage to 1.1V */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
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pmic_reg_write(p, REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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pmic_reg_read(p, REG_SW_1, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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pmic_reg_read(p, REG_SW_2, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_2, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, &mxc_ccm->cacrr);
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/* Set switchers in Auto in NORMAL mode & STANDBY mode */
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/* Setup the switcher mode for SW1 & SW2*/
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pmic_reg_read(p, REG_SW_4, &val);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(p, REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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pmic_reg_read(p, REG_SW_5, &val);
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val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
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(SWMODE_MASK << SWMODE4_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
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pmic_reg_write(p, REG_SW_5, val);
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
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pmic_reg_read(p, REG_SETTING_0, &val);
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val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
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val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
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pmic_reg_write(p, REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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pmic_reg_read(p, REG_SETTING_1, &val);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
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pmic_reg_write(p, REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(p, REG_MODE_1, val);
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udelay(200);
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gpio_direction_output(46, 0);
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/* Reset the ethernet controller over GPIO */
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writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(p, REG_MODE_1, val);
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udelay(500);
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gpio_set_value(46, 1);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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*cd = gpio_get_value(0);
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else
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*cd = gpio_get_value(6);
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
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index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX51_PIN_SD1_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_0,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
|
|
PAD_CTL_HYS_ENABLE);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_1,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
|
PAD_CTL_HYS_ENABLE);
|
|
break;
|
|
case 1:
|
|
mxc_request_iomux(MX51_PIN_SD2_CMD,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD2_CLK,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD2_DATA0,
|
|
IOMUX_CONFIG_ALT0);
|
|
mxc_request_iomux(MX51_PIN_SD2_DATA1,
|
|
IOMUX_CONFIG_ALT0);
|
|
mxc_request_iomux(MX51_PIN_SD2_DATA2,
|
|
IOMUX_CONFIG_ALT0);
|
|
mxc_request_iomux(MX51_PIN_SD2_DATA3,
|
|
IOMUX_CONFIG_ALT0);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
|
PAD_CTL_SRE_FAST);
|
|
mxc_request_iomux(MX51_PIN_SD2_CMD,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_6,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
|
|
PAD_CTL_HYS_ENABLE);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_5,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
|
|
PAD_CTL_HYS_ENABLE);
|
|
break;
|
|
default:
|
|
printf("Warning: you configured more ESDHC controller"
|
|
"(%d) as supported by the board(2)\n",
|
|
CONFIG_SYS_FSL_ESDHC_NUM);
|
|
return status;
|
|
}
|
|
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
|
|
}
|
|
return status;
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
setup_iomux_fec();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
system_rev = get_cpu_rev();
|
|
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_BOARD_LATE_INIT
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_MXC_SPI
|
|
setup_iomux_spi();
|
|
power_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: MX51EVK\n");
|
|
|
|
return 0;
|
|
}
|