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![Nikita Kiryanov](/assets/img/avatar_default.png)
Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3 based devices. This seems to be related to the following advisory which apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as OMAP4430 TRM: Advisory: I2C Module Does Not Allow 0-Byte Data Requests Details: When configured as the master, the I2C module does not allow 0-byte data transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause undefined behavior. Workaround(s): No workaround. Do not use 0-byte data requests. The writes in question are unnecessary from a functional point of view. Most of them are done after I/O has finished, and the only one that preceds I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before actual data transmission takes place. Therefore, remove all writes that zero the cnt register. Cc: Heiko Schocher <hs@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Tom Rini <trini@ti.com> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Enric Balletbo Serra <eballetbo@gmail.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com>
634 lines
17 KiB
C
634 lines
17 KiB
C
/*
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* Basic I2C functions
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*
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* Copyright (c) 2004 Texas Instruments
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*
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* This package is free software; you can redistribute it and/or
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* modify it under the terms of the license found in the file
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* named COPYING that should have accompanied this file.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Author: Jian Zhang jzhang@ti.com, Texas Instruments
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*
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* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
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* Rewritten to fit into the current U-Boot framework
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*
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* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
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*
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* Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
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* New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
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* (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
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* OMAPs and derivatives as well. The only anticipated exception would
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* be the OMAP2420, which shall require driver modification.
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* - Rewritten i2c_read to operate correctly with all types of chips
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* (old function could not read consistent data from some I2C slaves).
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* - Optimized i2c_write.
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* - New i2c_probe, performs write access vs read. The old probe could
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* hang the system under certain conditions (e.g. unconfigured pads).
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* - The read/write/probe functions try to identify unconfigured bus.
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* - Status functions now read irqstatus_raw as per TRM guidelines
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* (except for OMAP243X and OMAP34XX).
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* - Driver now supports up to I2C5 (OMAP5).
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/i2c.h>
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#include <asm/io.h>
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#include "omap24xx_i2c.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_TIMEOUT 1000
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/* Absolutely safe for status update at 100 kHz I2C: */
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#define I2C_WAIT 200
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static int wait_for_bb(struct i2c_adapter *adap);
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static struct i2c *omap24_get_base(struct i2c_adapter *adap);
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static u16 wait_for_event(struct i2c_adapter *adap);
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static void flush_fifo(struct i2c_adapter *adap);
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static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int psc, fsscll, fssclh;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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int timeout = I2C_TIMEOUT;
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/* Only handle standard, fast and high speeds */
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if ((speed != OMAP_I2C_STANDARD) &&
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(speed != OMAP_I2C_FAST_MODE) &&
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(speed != OMAP_I2C_HIGH_SPEED)) {
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printf("Error : I2C unsupported speed %d\n", speed);
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return;
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}
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psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
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psc -= 1;
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if (psc < I2C_PSC_MIN) {
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printf("Error : I2C unsupported prescalar %d\n", psc);
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return;
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}
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if (speed == OMAP_I2C_HIGH_SPEED) {
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/* High speed */
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/* For first phase of HS mode */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
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(2 * OMAP_I2C_FAST_MODE);
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fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
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fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing first phase clock\n");
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return;
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}
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/* For second phase of HS mode */
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hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
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hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing second phase clock\n");
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return;
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}
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scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
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sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
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} else {
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/* Standard and fast speed */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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fsscll -= I2C_FASTSPEED_SCLL_TRIM;
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fssclh -= I2C_FASTSPEED_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing clock\n");
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return;
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}
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scll = (unsigned int)fsscll;
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sclh = (unsigned int)fssclh;
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}
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if (readw(&i2c_base->con) & I2C_CON_EN) {
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writew(0, &i2c_base->con);
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udelay(50000);
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}
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writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
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udelay(1000);
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writew(I2C_CON_EN, &i2c_base->con);
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while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
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if (timeout <= 0) {
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puts("ERROR: Timeout in soft-reset\n");
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return;
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}
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udelay(1000);
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}
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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/* own address */
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writew(slaveadd, &i2c_base->oa);
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writew(I2C_CON_EN, &i2c_base->con);
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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/*
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* Have to enable interrupts for OMAP2/3, these IPs don't have
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* an 'irqstatus_raw' register and we shall have to poll 'stat'
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*/
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writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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#endif
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udelay(1000);
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flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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}
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static void flush_fifo(struct i2c_adapter *adap)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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u16 stat;
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/* note: if you try and read data when its not there or ready
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* you get a bus error
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*/
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while (1) {
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stat = readw(&i2c_base->stat);
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if (stat == I2C_STAT_RRDY) {
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readb(&i2c_base->data);
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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udelay(1000);
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} else
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break;
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}
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}
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/*
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* i2c_probe: Use write access. Allows to identify addresses that are
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* write-only (like the config register of dual-port EEPROMs)
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*/
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static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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u16 status;
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int res = 1; /* default = fail */
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if (chip == readw(&i2c_base->oa))
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return res;
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/* Wait until bus is free */
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if (wait_for_bb(adap))
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return res;
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/* No data transfer, slave addr only */
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writew(chip, &i2c_base->sa);
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/* Stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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status = wait_for_event(adap);
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if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
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/*
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* With current high-level command implementation, notifying
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* the user shall flood the console with 127 messages. If
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* silent exit is desired upon unconfigured bus, remove the
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* following 'if' section:
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*/
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if (status == I2C_STAT_XRDY)
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printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
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adap->hwadapnr, status);
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goto pr_exit;
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}
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/* Check for ACK (!NAK) */
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if (!(status & I2C_STAT_NACK)) {
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res = 0; /* Device found */
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udelay(I2C_WAIT); /* Required by AM335X in SPL */
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/* Abort transfer (force idle state) */
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writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
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udelay(1000);
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con); /* STP */
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}
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pr_exit:
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flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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return res;
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}
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/*
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* i2c_read: Function now uses a single I2C read transaction with bulk transfer
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* of the requested number of bytes (note that the 'i2c md' command
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* limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
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* defined in the board config header, this transaction shall be with
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* Repeated Start (Sr) between the address and data phases; otherwise
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* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
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* The address (reg offset) may be 0, 1 or 2 bytes long.
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* Function now reads correctly from chips that return more than one
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* byte of data per addressed register (like TI temperature sensors),
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* or that do not need a register address at all (such as some clock
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* distributors).
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*/
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static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int i2c_error = 0;
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u16 status;
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if (alen < 0) {
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puts("I2C read: addr len < 0\n");
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return 1;
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}
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if (len < 0) {
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puts("I2C read: data len < 0\n");
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return 1;
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}
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if (buffer == NULL) {
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puts("I2C read: NULL pointer passed\n");
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return 1;
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}
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if (alen > 2) {
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printf("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if (addr + len > (1 << 16)) {
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puts("I2C read: address out of range\n");
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return 1;
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}
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/* Wait until bus not busy */
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if (wait_for_bb(adap))
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return 1;
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/* Zero, one or two bytes reg address (offset) */
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writew(alen, &i2c_base->cnt);
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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if (alen) {
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/* Must write reg offset first */
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#ifdef CONFIG_I2C_REPEATED_START
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/* No stop bit, use Repeated Start (Sr) */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX, &i2c_base->con);
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#else
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/* Stop - Start (P-S) */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
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I2C_CON_TRX, &i2c_base->con);
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#endif
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/* Send register offset */
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while (1) {
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status = wait_for_event(adap);
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/* Try to identify bus that is not padconf'd for I2C */
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
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adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
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status);
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goto rd_exit;
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}
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if (alen) {
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if (status & I2C_STAT_XRDY) {
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alen--;
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/* Do we have to use byte access? */
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writeb((addr >> (8 * alen)) & 0xff,
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&i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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}
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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/* Read len bytes from slave */
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writew(len, &i2c_base->cnt);
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/* Need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* Receive data */
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while (1) {
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status = wait_for_event(adap);
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/*
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* Try to identify bus that is not padconf'd for I2C. This
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* state could be left over from previous transactions if
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* the address phase is skipped due to alen=0.
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*/
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
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adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto rd_exit;
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}
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if (status & I2C_STAT_RRDY) {
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*buffer++ = readb(&i2c_base->data);
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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rd_exit:
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flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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return i2c_error;
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}
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/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
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static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int i;
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u16 status;
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int i2c_error = 0;
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if (alen < 0) {
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puts("I2C write: addr len < 0\n");
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return 1;
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}
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if (len < 0) {
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puts("I2C write: data len < 0\n");
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return 1;
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}
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if (buffer == NULL) {
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puts("I2C write: NULL pointer passed\n");
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return 1;
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}
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if (alen > 2) {
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printf("I2C write: addr len %d not supported\n", alen);
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return 1;
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}
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if (addr + len > (1 << 16)) {
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printf("I2C write: address 0x%x + 0x%x out of range\n",
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addr, len);
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return 1;
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}
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/* Wait until bus not busy */
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if (wait_for_bb(adap))
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return 1;
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/* Start address phase - will write regoffset + len bytes data */
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writew(alen + len, &i2c_base->cnt);
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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/* Stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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while (alen) {
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/* Must write reg offset (one or two bytes) */
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status = wait_for_event(adap);
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/* Try to identify bus that is not padconf'd for I2C */
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
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adap->hwadapnr, status);
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goto wr_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
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status);
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goto wr_exit;
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}
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if (status & I2C_STAT_XRDY) {
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alen--;
|
|
writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
|
|
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
|
} else {
|
|
i2c_error = 1;
|
|
printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
}
|
|
/* Address phase is over, now write data */
|
|
for (i = 0; i < len; i++) {
|
|
status = wait_for_event(adap);
|
|
if (status == 0 || status & I2C_STAT_NACK) {
|
|
i2c_error = 1;
|
|
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
if (status & I2C_STAT_XRDY) {
|
|
writeb(buffer[i], &i2c_base->data);
|
|
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
|
} else {
|
|
i2c_error = 1;
|
|
printf("i2c_write: bus not ready for data Tx (i=%d)\n",
|
|
i);
|
|
goto wr_exit;
|
|
}
|
|
}
|
|
|
|
wr_exit:
|
|
flush_fifo(adap);
|
|
writew(0xFFFF, &i2c_base->stat);
|
|
return i2c_error;
|
|
}
|
|
|
|
/*
|
|
* Wait for the bus to be free by checking the Bus Busy (BB)
|
|
* bit to become clear
|
|
*/
|
|
static int wait_for_bb(struct i2c_adapter *adap)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
int timeout = I2C_TIMEOUT;
|
|
u16 stat;
|
|
|
|
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
|
|
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
|
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
|
|
#else
|
|
/* Read RAW status */
|
|
while ((stat = readw(&i2c_base->irqstatus_raw) &
|
|
I2C_STAT_BB) && timeout--) {
|
|
#endif
|
|
writew(stat, &i2c_base->stat);
|
|
udelay(I2C_WAIT);
|
|
}
|
|
|
|
if (timeout <= 0) {
|
|
printf("Timed out in wait_for_bb: status=%04x\n",
|
|
stat);
|
|
return 1;
|
|
}
|
|
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Wait for the I2C controller to complete current action
|
|
* and update status
|
|
*/
|
|
static u16 wait_for_event(struct i2c_adapter *adap)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
u16 status;
|
|
int timeout = I2C_TIMEOUT;
|
|
|
|
do {
|
|
udelay(I2C_WAIT);
|
|
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
|
status = readw(&i2c_base->stat);
|
|
#else
|
|
/* Read RAW status */
|
|
status = readw(&i2c_base->irqstatus_raw);
|
|
#endif
|
|
} while (!(status &
|
|
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
|
|
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
|
|
I2C_STAT_AL)) && timeout--);
|
|
|
|
if (timeout <= 0) {
|
|
printf("Timed out in wait_for_event: status=%04x\n",
|
|
status);
|
|
/*
|
|
* If status is still 0 here, probably the bus pads have
|
|
* not been configured for I2C, and/or pull-ups are missing.
|
|
*/
|
|
printf("Check if pads/pull-ups of bus %d are properly configured\n",
|
|
adap->hwadapnr);
|
|
writew(0xFFFF, &i2c_base->stat);
|
|
status = 0;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static struct i2c *omap24_get_base(struct i2c_adapter *adap)
|
|
{
|
|
switch (adap->hwadapnr) {
|
|
case 0:
|
|
return (struct i2c *)I2C_BASE1;
|
|
break;
|
|
case 1:
|
|
return (struct i2c *)I2C_BASE2;
|
|
break;
|
|
#if (I2C_BUS_MAX > 2)
|
|
case 2:
|
|
return (struct i2c *)I2C_BASE3;
|
|
break;
|
|
#if (I2C_BUS_MAX > 3)
|
|
case 3:
|
|
return (struct i2c *)I2C_BASE4;
|
|
break;
|
|
#if (I2C_BUS_MAX > 4)
|
|
case 4:
|
|
return (struct i2c *)I2C_BASE5;
|
|
break;
|
|
#endif
|
|
#endif
|
|
#endif
|
|
default:
|
|
printf("wrong hwadapnr: %d\n", adap->hwadapnr);
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE,
|
|
0)
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED1,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE1,
|
|
1)
|
|
#if (I2C_BUS_MAX > 2)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED2,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE2,
|
|
2)
|
|
#if (I2C_BUS_MAX > 3)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED3,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE3,
|
|
3)
|
|
#if (I2C_BUS_MAX > 4)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED4,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE4,
|
|
4)
|
|
#endif
|
|
#endif
|
|
#endif
|