mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 06:36:16 +09:00
9aea95307f
- support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration space access support for MPC85xx PCI Bridge
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*/
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#include <common.h>
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#include <asm/cpm_85xx.h>
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#include <pci.h>
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#if defined(CONFIG_PCI)
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void
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pci_mpc85xx_init(struct pci_controller *hose)
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{
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volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
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volatile ccsr_pcix_t *pcix = &immap->im_pcix;
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u16 reg16;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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pci_setup_indirect(hose,
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(CFG_IMMR+0x8000),
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(CFG_IMMR+0x8004));
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
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pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcix->potear1 = 0x00000000;
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pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = 0x8004401c; /* 512M MEM space */
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pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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pcix->powar2 = 0x80088017; /* 16M IO space */
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = 0xa0F5501f;
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI */
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