mirror of
https://github.com/brain-hackers/u-boot-brain
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![wdenk](/assets/img/avatar_default.png)
before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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long int spd_sdram (void);
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#include <common.h>
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#include <asm/processor.h>
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int board_early_init_f (void)
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{
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000010);
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mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
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mtdcr (uictr, 0x00000010); /* set int trigger levels */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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#if 0
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#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
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/* CS1 */
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/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
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mtebc (pb1ap, 0x02815480);
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mtebc (pb1cr, 0xF0018000);
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p = (unsigned int*)0xEF600708;
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t = *p;
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t = t | 0x00000400;
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*p = t;
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/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
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mtebc (pb2ap, 0x04815A80);
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mtebc (pb2cr, 0xF0118000);
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/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
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mtebc (pb3ap, 0x01815280);
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mtebc (pb3cr, 0xF0218000);
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/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
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mtebc (pb7ap, 0x01815280);
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mtebc (pb7cr, 0xF0318000);
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/* set UART1 control to select CTS/RTS */
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#define FPGA_BRDC 0xF0300004
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*(volatile char *) (FPGA_BRDC) |= 0x1;
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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unsigned char *s = getenv ("serial#");
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puts ("Board: IBM 405EP Eval Board");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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return (0);
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}
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/* -------------------------------------------------------------------------
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initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
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the necessary info for SDRAM controller configuration
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------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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long int ret;
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ret = spd_sdram ();
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return ret;
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: xxx MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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