mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 14:43:49 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
163 lines
4.6 KiB
C
163 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _PFE_H_
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#define _PFE_H_
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#include <elf.h>
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#include "cbus.h"
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#define PFE_RESET_WA
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#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
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/* Only valid for mem access register interface */
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#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
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#define CLASS_DMEM_SIZE 0x00002000
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#define CLASS_IMEM_SIZE 0x00008000
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#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
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/* Only valid for mem access register interface */
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#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
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#define TMU_DMEM_SIZE 0x00000800
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#define TMU_IMEM_SIZE 0x00002000
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#define UTIL_DMEM_BASE_ADDR 0x00000000
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#define UTIL_DMEM_SIZE 0x00002000
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#define PE_LMEM_BASE_ADDR 0xc3010000
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#define PE_LMEM_SIZE 0x8000
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#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
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#define DMEM_BASE_ADDR 0x00000000
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#define DMEM_SIZE 0x2000 /* TMU has less... */
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#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
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#define PMEM_BASE_ADDR 0x00010000
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#define PMEM_SIZE 0x8000 /* TMU has less... */
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#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
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/* Memory ranges check from PE point of view/memory map */
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#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
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(((unsigned long)(addr) +\
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(len)) <= DMEM_END))
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#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
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(((unsigned long)(addr) +\
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(len)) <= PMEM_END))
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#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
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) && (((unsigned long)(addr)\
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+ (len)) <= PE_LMEM_END))
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#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
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CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
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(((unsigned long)(addr) + (len)) <=\
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CBUS_VIRT_TO_PFE(LMEM_END)))
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#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
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PFE_DDR_PHYS_BASE_ADDR) &&\
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(((unsigned long)(addr) + (len)) <=\
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PFE_DDR_PHYS_END))
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/* Host View Address */
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extern void *ddr_pfe_base_addr;
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/* PFE View Address */
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/* DDR physical base address as seen by PE's. */
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#define PFE_DDR_PHYS_BASE_ADDR 0x03800000
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#define PFE_DDR_PHYS_SIZE 0xC000000
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#define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
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/* CBUS physical base address as seen by PE's. */
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#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
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/* Host<->PFE Mapping */
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#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
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#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
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PFE_CBUS_PHYS_BASE_ADDR)
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#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
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CBUS_BASE_ADDR)
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enum {
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CLASS0_ID = 0,
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CLASS1_ID,
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CLASS2_ID,
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CLASS3_ID,
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CLASS4_ID,
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CLASS5_ID,
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TMU0_ID,
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TMU1_ID,
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TMU2_ID,
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TMU3_ID,
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MAX_PE
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};
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#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
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| BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
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BIT(CLASS5_ID))
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#define CLASS_MAX_ID CLASS5_ID
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#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
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#define TMU_MAX_ID TMU3_ID
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/*
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* PE information.
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* Structure containing PE's specific information. It is used to create
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* generic C functions common to all PEs.
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* Before using the library functions this structure needs to be
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* initialized with the different registers virtual addresses
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* (according to the ARM MMU mmaping). The default initialization supports a
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* virtual == physical mapping.
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*
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*/
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struct pe_info {
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u32 dmem_base_addr; /* PE's dmem base address */
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u32 pmem_base_addr; /* PE's pmem base address */
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u32 pmem_size; /* PE's pmem size */
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void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
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* register address
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*/
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void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
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* register address
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*/
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void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
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* register address
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*/
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};
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void pe_lmem_read(u32 *dst, u32 len, u32 offset);
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void pe_lmem_write(u32 *src, u32 len, u32 offset);
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u32 pe_pmem_read(int id, u32 addr, u8 size);
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void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
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u32 pe_dmem_read(int id, u32 addr, u8 size);
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int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
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void pfe_lib_init(void);
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void bmu_init(void *base, struct bmu_cfg *cfg);
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void bmu_enable(void *base);
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void gpi_init(void *base, struct gpi_cfg *cfg);
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void gpi_enable(void *base);
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void gpi_disable(void *base);
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void class_init(struct class_cfg *cfg);
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void class_enable(void);
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void class_disable(void);
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void tmu_init(struct tmu_cfg *cfg);
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void tmu_enable(u32 pe_mask);
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void tmu_disable(u32 pe_mask);
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void hif_init(void);
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void hif_tx_enable(void);
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void hif_tx_disable(void);
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void hif_rx_enable(void);
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void hif_rx_disable(void);
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void hif_rx_desc_disable(void);
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#endif /* _PFE_H_ */
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