mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 16:40:44 +09:00
9a5bbdfd1a
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
9 lines
346 B
Plaintext
9 lines
346 B
Plaintext
config SPL_ALTERA_SDRAM
|
|
bool "SoCFPGA DDR SDRAM driver in SPL"
|
|
depends on SPL
|
|
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
|
|
select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
|
|
select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
|
|
help
|
|
Enable DDR SDRAM controller for the SoCFPGA devices.
|