mirror of
https://github.com/brain-hackers/u-boot-brain
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afabb498b7
This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
261 lines
6.6 KiB
C
261 lines
6.6 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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/* Only compile this file for boards with GPIO support */
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#if defined(GPIO0_BASE)
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#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
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gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
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#endif
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#if defined(GPIO0_OSRL)
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/* Only some 4xx variants support alternate funtions on the GPIO's */
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void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
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{
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u32 mask;
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u32 mask2;
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u32 val;
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u32 offs = 0;
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u32 offs2 = 0;
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int pin2 = pin << 1;
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if (pin >= GPIO_MAX) {
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offs = 0x100;
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pin -= GPIO_MAX;
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}
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if (pin >= GPIO_MAX/2) {
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offs2 = 0x4;
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pin2 = (pin - GPIO_MAX/2) << 1;
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}
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mask = 0x80000000 >> pin;
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mask2 = 0xc0000000 >> pin2;
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/* first set TCR to 0 */
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out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
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if (in_out == GPIO_OUT) {
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val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
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switch (gpio_alt) {
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case GPIO_ALT1:
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val |= GPIO_ALT1_SEL >> pin2;
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break;
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case GPIO_ALT2:
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val |= GPIO_ALT2_SEL >> pin2;
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break;
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case GPIO_ALT3:
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val |= GPIO_ALT3_SEL >> pin2;
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break;
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}
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out_be32((void *)GPIO0_OSRL + offs + offs2, val);
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/* setup requested output value */
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if (out_val == GPIO_OUT_0)
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out_be32((void *)GPIO0_OR + offs,
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in_be32((void *)GPIO0_OR + offs) & ~mask);
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else if (out_val == GPIO_OUT_1)
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out_be32((void *)GPIO0_OR + offs,
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in_be32((void *)GPIO0_OR + offs) | mask);
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/* now configure TCR to drive output if selected */
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out_be32((void *)GPIO0_TCR + offs,
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in_be32((void *)GPIO0_TCR + offs) | mask);
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} else {
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val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
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val |= GPIO_IN_SEL >> pin2;
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out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
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}
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}
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#endif /* GPIO_OSRL */
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void gpio_write_bit(int pin, int val)
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{
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u32 offs = 0;
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if (pin >= GPIO_MAX) {
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offs = 0x100;
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pin -= GPIO_MAX;
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}
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if (val)
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out_be32((void *)GPIO0_OR + offs,
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in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
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else
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out_be32((void *)GPIO0_OR + offs,
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in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
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}
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int gpio_read_out_bit(int pin)
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{
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u32 offs = 0;
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if (pin >= GPIO_MAX) {
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offs = 0x100;
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pin -= GPIO_MAX;
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}
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return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
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}
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int gpio_read_in_bit(int pin)
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{
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u32 offs = 0;
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if (pin >= GPIO_MAX) {
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offs = 0x100;
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pin -= GPIO_MAX;
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}
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return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
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}
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#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
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void gpio_set_chip_configuration(void)
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{
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unsigned char i=0, j=0, offs=0, gpio_core;
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unsigned long reg, core_add;
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for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
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j = 0;
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offs = 0;
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/* GPIO config of the GPIOs 0 to 31 */
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for (i=0; i<GPIO_MAX; i++, j++) {
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if (i == GPIO_MAX/2) {
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offs = 4;
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j = i-16;
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}
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core_add = gpio_tab[gpio_core][i].add;
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if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
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(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
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switch (gpio_tab[gpio_core][i].alt_nb) {
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case GPIO_SEL:
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break;
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case GPIO_ALT1:
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reg = in_be32((void *)GPIO_IS1(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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reg = reg | (GPIO_IN_SEL >> (j*2));
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out_be32((void *)GPIO_IS1(core_add+offs), reg);
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break;
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case GPIO_ALT2:
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reg = in_be32((void *)GPIO_IS2(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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reg = reg | (GPIO_IN_SEL >> (j*2));
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out_be32((void *)GPIO_IS2(core_add+offs), reg);
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break;
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case GPIO_ALT3:
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reg = in_be32((void *)GPIO_IS3(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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reg = reg | (GPIO_IN_SEL >> (j*2));
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out_be32((void *)GPIO_IS3(core_add+offs), reg);
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break;
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}
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}
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if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
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(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
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u32 gpio_alt_sel = 0;
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switch (gpio_tab[gpio_core][i].alt_nb) {
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case GPIO_SEL:
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/*
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* Setup output value
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* 1 -> high level
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* 0 -> low level
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* else -> don't touch
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*/
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reg = in_be32((void *)GPIO_OR(core_add));
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if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
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reg |= (0x80000000 >> (i));
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else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
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reg &= ~(0x80000000 >> (i));
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out_be32((void *)GPIO_OR(core_add), reg);
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reg = in_be32((void *)GPIO_TCR(core_add)) |
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(0x80000000 >> (i));
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out_be32((void *)GPIO_TCR(core_add), reg);
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reg = in_be32((void *)GPIO_OS(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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out_be32((void *)GPIO_OS(core_add+offs), reg);
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reg = in_be32((void *)GPIO_TS(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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out_be32((void *)GPIO_TS(core_add+offs), reg);
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break;
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case GPIO_ALT1:
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gpio_alt_sel = GPIO_ALT1_SEL;
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break;
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case GPIO_ALT2:
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gpio_alt_sel = GPIO_ALT2_SEL;
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break;
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case GPIO_ALT3:
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gpio_alt_sel = GPIO_ALT3_SEL;
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break;
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}
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if (0 != gpio_alt_sel) {
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reg = in_be32((void *)GPIO_OS(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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reg = reg | (gpio_alt_sel >> (j*2));
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out_be32((void *)GPIO_OS(core_add+offs), reg);
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if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
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reg = in_be32((void *)GPIO_TCR(core_add))
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| (0x80000000 >> (i));
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out_be32((void *)GPIO_TCR(core_add), reg);
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reg = in_be32((void *)GPIO_TS(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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out_be32((void *)GPIO_TS(core_add+offs), reg);
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} else {
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reg = in_be32((void *)GPIO_TCR(core_add))
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& ~(0x80000000 >> (i));
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out_be32((void *)GPIO_TCR(core_add), reg);
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reg = in_be32((void *)GPIO_TS(core_add+offs))
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& ~(GPIO_MASK >> (j*2));
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reg = reg | (gpio_alt_sel >> (j*2));
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out_be32((void *)GPIO_TS(core_add+offs), reg);
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}
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}
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}
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}
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}
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}
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#endif /* GPIO0_BASE */
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#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
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