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https://github.com/brain-hackers/u-boot-brain
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3a649407a4
Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for various reasons. We also have cases where we only build SPL in Thumb2 mode due to size constraints and wish to build the rest of the system in ARM mode. So in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to control if we build everything or just SPL (or in theory, just U-Boot) in Thumb2 mode. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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#include <asm/system.h>
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#ifndef CONFIG_ARM64
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/*
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* Invalidate L2 Cache using co-proc instruction
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*/
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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void invalidate_l2_cache(void);
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#else
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static inline void invalidate_l2_cache(void)
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{
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unsigned int val=0;
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asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
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: : "r" (val) : "cc");
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isb();
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}
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#endif
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int check_cache_range(unsigned long start, unsigned long stop);
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void l2_cache_enable(void);
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void l2_cache_disable(void);
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void set_section_dcache(int section, enum dcache_option option);
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void arm_init_before_mmu(void);
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void arm_init_domains(void);
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void cpu_cache_initialization(void);
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void dram_bank_mmu_setup(int bank);
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#endif
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/*
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* The value of the largest data cache relevant to DMA operations shall be set
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* for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
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* value than found in the L1 cache but this is OK to use in terms of
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* alignment.
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*/
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#endif /* _ASM_CACHE_H */
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