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![Tom Warren](/assets/img/avatar_default.png)
All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
27 lines
820 B
C
27 lines
820 B
C
/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA210_SYSCTR_H_
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#define _TEGRA210_SYSCTR_H_
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struct sysctr_ctlr {
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u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
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u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
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u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
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u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
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u32 reserved1[4]; /* 0x10 - 0x1C */
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u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
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u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
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u32 reserved2[1002]; /* 0x28 - 0xFCC */
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u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
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};
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#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
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#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
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#endif /* _TEGRA210_SYSCTR_H_ */
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