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https://github.com/brain-hackers/u-boot-brain
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30ca20234e
Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
129 lines
4.6 KiB
C
129 lines
4.6 KiB
C
/*
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* Sunxi platform timing controller register and constant defines
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _LCDC_H
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#define _LCDC_H
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#include <fdtdec.h>
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struct sunxi_lcdc_reg {
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u32 ctrl; /* 0x00 */
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u32 int0; /* 0x04 */
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u32 int1; /* 0x08 */
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u8 res0[0x04]; /* 0x0c */
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u32 tcon0_frm_ctrl; /* 0x10 */
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u32 tcon0_frm_seed[6]; /* 0x14 */
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u32 tcon0_frm_table[4]; /* 0x2c */
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u8 res1[4]; /* 0x3c */
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u32 tcon0_ctrl; /* 0x40 */
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u32 tcon0_dclk; /* 0x44 */
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u32 tcon0_timing_active; /* 0x48 */
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u32 tcon0_timing_h; /* 0x4c */
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u32 tcon0_timing_v; /* 0x50 */
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u32 tcon0_timing_sync; /* 0x54 */
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u32 tcon0_hv_intf; /* 0x58 */
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u8 res2[0x04]; /* 0x5c */
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u32 tcon0_cpu_intf; /* 0x60 */
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u32 tcon0_cpu_wr_dat; /* 0x64 */
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u32 tcon0_cpu_rd_dat0; /* 0x68 */
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u32 tcon0_cpu_rd_dat1; /* 0x6c */
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u32 tcon0_ttl_timing0; /* 0x70 */
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u32 tcon0_ttl_timing1; /* 0x74 */
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u32 tcon0_ttl_timing2; /* 0x78 */
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u32 tcon0_ttl_timing3; /* 0x7c */
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u32 tcon0_ttl_timing4; /* 0x80 */
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u32 tcon0_lvds_intf; /* 0x84 */
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u32 tcon0_io_polarity; /* 0x88 */
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u32 tcon0_io_tristate; /* 0x8c */
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u32 tcon1_ctrl; /* 0x90 */
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u32 tcon1_timing_source; /* 0x94 */
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u32 tcon1_timing_scale; /* 0x98 */
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u32 tcon1_timing_out; /* 0x9c */
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u32 tcon1_timing_h; /* 0xa0 */
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u32 tcon1_timing_v; /* 0xa4 */
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u32 tcon1_timing_sync; /* 0xa8 */
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u8 res3[0x44]; /* 0xac */
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u32 tcon1_io_polarity; /* 0xf0 */
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u32 tcon1_io_tristate; /* 0xf4 */
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u8 res4[0x108]; /* 0xf8 */
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u32 mux_ctrl; /* 0x200 */
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u8 res5[0x1c]; /* 0x204 */
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u32 lvds_ana0; /* 0x220 */
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u32 lvds_ana1; /* 0x224 */
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};
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/*
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* LCDC register constants.
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*/
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#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
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#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
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#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
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#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
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#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
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#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
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#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
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#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
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#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
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#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
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#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
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#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
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#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
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#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
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#else
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
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#endif
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#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
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#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
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#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
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#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
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#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
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#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_LVDS_ANA0 0x40040320
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#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
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#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
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#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
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#else
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#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
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#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
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#endif
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#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
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#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
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void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
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void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
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void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct display_timing *mode,
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int clk_div, bool for_ext_vga_dac,
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int depth, int dclk_phase);
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void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct display_timing *mode,
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bool ext_hvsync, bool is_composite);
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#endif /* _LCDC_H */
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