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https://github.com/brain-hackers/u-boot-brain
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83843c9b3a
The Allwinner A64 SoC starts execution in AArch32 mode, and both the boot ROM and Allwinner's boot0 keep running in this mode. So U-Boot gets entered in 32-bit, although we want it to run in AArch64. By using a "magic" instruction, which happens to be an almost-NOP in AArch64 and a branch in AArch32, we differentiate between being entered in 64-bit or 32-bit mode. If in 64-bit mode, we proceed with the branch to reset, but in 32-bit mode we trigger an RMR write to bring the core into AArch64/EL3 and re-enter U-Boot at CONFIG_SYS_TEXT_BASE. This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode, so we can use the same start code for the SPL and the U-Boot proper. We use the existing custom header (boot0.h) functionality, but restrict the existing boot0 header reservation to the non-SPL build now. A SPL wouldn't need such header anyway. This allows to have both options defined and lets us use one for the SPL and the other for U-Boot proper. Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original ARM assembly code and instructions how to re-generate the encoded version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Configuration settings for the Allwinner A64 (sun50i) CPU
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
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/* reserve space for BOOT0 header information */
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b reset
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.space 1532
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#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
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/*
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* Switch into AArch64 if needed.
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* Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
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*/
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tst x0, x0 // this is "b #0x84" in ARM
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b reset
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.space 0x7c
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.word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0
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.word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
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.word 0xe5810000 // str r0, [r1]
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.word 0xf57ff04f // dsb sy
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.word 0xf57ff06f // isb sy
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.word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
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.word 0xe3800003 // orr r0, r0, #3
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.word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
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.word 0xf57ff06f // isb sy
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.word 0xe320f003 // wfi
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.word 0xeafffffd // b @wfi
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.word 0x017000a0 // writeable RVBAR mapping address
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#ifdef CONFIG_SPL_BUILD
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.word CONFIG_SPL_TEXT_BASE
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#else
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.word CONFIG_SYS_TEXT_BASE
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#endif
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#else
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/* normal execution */
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b reset
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#endif
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