mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-25 11:28:51 +09:00
a982d5156d
configure_l2ctlr will be shared between SPL and TPL so move them into asm/arch/sys_proto.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
34 lines
684 B
C
34 lines
684 B
C
/*
|
|
* (C) Copyright 2016 Rockchip Electronics Co.,Ltd
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _ASM_ARCH_SYS_PROTO_H
|
|
#define _ASM_ARCH_SYS_PROTO_H
|
|
|
|
#ifdef CONFIG_ROCKCHIP_RK3288
|
|
#include <asm/armv7.h>
|
|
|
|
static void configure_l2ctlr(void)
|
|
{
|
|
uint32_t l2ctlr;
|
|
|
|
l2ctlr = read_l2ctlr();
|
|
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
|
|
|
|
/*
|
|
* Data RAM write latency: 2 cycles
|
|
* Data RAM read latency: 2 cycles
|
|
* Data RAM setup latency: 1 cycle
|
|
* Tag RAM write latency: 1 cycle
|
|
* Tag RAM read latency: 1 cycle
|
|
* Tag RAM setup latency: 1 cycle
|
|
*/
|
|
l2ctlr |= (1 << 3 | 1 << 0);
|
|
write_l2ctlr(l2ctlr);
|
|
}
|
|
#endif /* CONFIG_ROCKCHIP_RK3288 */
|
|
|
|
#endif /* _ASM_ARCH_SYS_PROTO_H */
|