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![Kever Yang](/assets/img/avatar_default.png)
Add driver for rk322x to support sdram initialize in SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
582 lines
11 KiB
C
582 lines
11 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SDRAM_RK322X_H
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#define _ASM_ARCH_SDRAM_RK322X_H
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#include <common.h>
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enum {
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DDR3 = 3,
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LPDDR2 = 5,
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LPDDR3 = 6,
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UNUSED = 0xFF,
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};
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struct rk322x_sdram_channel {
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/*
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* bit width in address, eg:
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* 8 banks using 3 bit to address,
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* 2 cs using 1 bit to address.
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*/
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u8 rank;
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u8 col;
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u8 bk;
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u8 bw;
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u8 dbw;
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u8 row_3_4;
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u8 cs0_row;
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u8 cs1_row;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/*
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* For of-platdata, which would otherwise convert this into two
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* byte-swapped integers. With a size of 9 bytes, this struct will
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* appear in of-platdata as a byte array.
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*
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* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
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*/
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u8 dummy;
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#endif
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};
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struct rk322x_ddr_pctl {
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u32 scfg;
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[(0x40 - 0x10) / 4];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 cmdtstaten;
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u32 reserved1[(0x60 - 0x54) / 4];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[(0x7c - 0x6c) / 4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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u32 mstat;
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u32 lpddr2zqcfg;
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u32 reserved3;
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u32 dtupdes;
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u32 dtuna;
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u32 dtune;
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u32 dtuprd0;
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u32 dtuprd1;
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[(0xc0 - 0xb4) / 4];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 tref_mem_ddr3;
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u32 reserved5[(0x180 - 0x14c) / 4];
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u32 ecccfg;
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u32 ecctst;
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u32 eccclr;
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u32 ecclog;
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u32 reserved6[(0x200 - 0x190) / 4];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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u32 dtuectl;
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u32 dtuwd0;
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u32 dtuwd1;
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u32 dtuwd2;
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u32 dtuwd3;
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u32 dtuwdm;
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u32 dturd0;
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u32 dturd1;
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u32 dturd2;
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u32 dturd3;
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u32 dtulfsrwd;
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u32 dtulfsrrd;
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u32 dtueaf;
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/* dfi control registers */
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u32 dfitctrldelay;
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u32 dfiodtcfg;
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u32 dfiodtcfg1;
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u32 dfiodtrankmap;
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/* dfi write data registers */
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u32 dfitphywrdata;
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u32 dfitphywrlat;
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u32 reserved7[(0x260 - 0x258) / 4];
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[(0x270 - 0x268) / 4];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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u32 dfitphyupdtype3;
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u32 dfitctrlupdmin;
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u32 dfitctrlupdmax;
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u32 dfitctrlupddly;
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u32 reserved9;
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[(0x2ac - 0x29c) / 4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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u32 dfitrrdlvlen;
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u32 dfitrrdlvlgateen;
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u32 dfiststat0;
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u32 dfistcfg0;
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u32 dfistcfg1;
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u32 reserved11;
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u32 dfitdramclken;
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u32 dfitdramclkdis;
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[(0x2f0 - 0x2e4) / 4];
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u32 dfilpcfg0;
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u32 reserved13[(0x300 - 0x2f4) / 4];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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u32 dfitrrdlvlresp0;
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u32 dfitrrdlvlresp1;
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u32 dfitrrdlvlresp2;
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u32 dfitrwrlvldelay0;
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u32 dfitrwrlvldelay1;
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u32 dfitrwrlvldelay2;
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u32 dfitrrdlvldelay0;
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u32 dfitrrdlvldelay1;
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u32 dfitrrdlvldelay2;
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u32 dfitrrdlvlgatedelay0;
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[(0x3f8 - 0x340) / 4];
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u32 ipvr;
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u32 iptr;
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};
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check_member(rk322x_ddr_pctl, iptr, 0x03fc);
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struct rk322x_ddr_phy {
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u32 ddrphy_reg[0x100];
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};
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struct rk322x_pctl_timing {
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 trefi_mem_ddr3;
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};
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struct rk322x_phy_timing {
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u32 mr[4];
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u32 mr11;
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u32 bl;
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u32 cl_al;
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};
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struct rk322x_msch_timings {
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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u32 activate;
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u32 devtodev;
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};
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struct rk322x_service_sys {
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u32 id_coreid;
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u32 id_revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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u32 activate;
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u32 devtodev;
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};
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struct rk322x_base_params {
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struct rk322x_msch_timings noc_timing;
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u32 ddrconfig;
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u32 ddr_freq;
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u32 dramtype;
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/*
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* unused for rk322x
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*/
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u32 stride;
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u32 odt;
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};
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/* PCT_DFISTCFG0 */
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#define DFI_INIT_START BIT(0)
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#define DFI_DATA_BYTE_DISABLE_EN BIT(2)
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/* PCT_DFISTCFG1 */
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#define DFI_DRAM_CLK_SR_EN BIT(0)
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#define DFI_DRAM_CLK_DPD_EN BIT(1)
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/* PCT_DFISTCFG2 */
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#define DFI_PARITY_INTR_EN BIT(0)
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#define DFI_PARITY_EN BIT(1)
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/* PCT_DFILPCFG0 */
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#define TLP_RESP_TIME_SHIFT 16
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#define LP_SR_EN BIT(8)
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#define LP_PD_EN BIT(0)
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/* PCT_DFITCTRLDELAY */
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#define TCTRL_DELAY_TIME_SHIFT 0
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/* PCT_DFITPHYWRDATA */
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#define TPHY_WRDATA_TIME_SHIFT 0
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/* PCT_DFITPHYRDLAT */
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#define TPHY_RDLAT_TIME_SHIFT 0
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/* PCT_DFITDRAMCLKDIS */
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#define TDRAM_CLK_DIS_TIME_SHIFT 0
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/* PCT_DFITDRAMCLKEN */
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#define TDRAM_CLK_EN_TIME_SHIFT 0
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/* PCTL_DFIODTCFG */
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#define RANK0_ODT_WRITE_SEL BIT(3)
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#define RANK1_ODT_WRITE_SEL BIT(11)
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/* PCTL_DFIODTCFG1 */
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#define ODT_LEN_BL8_W_SHIFT 16
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/* PUBL_ACDLLCR */
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#define ACDLLCR_DLLDIS BIT(31)
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#define ACDLLCR_DLLSRST BIT(30)
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/* PUBL_DXDLLCR */
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#define DXDLLCR_DLLDIS BIT(31)
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#define DXDLLCR_DLLSRST BIT(30)
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/* PUBL_DLLGCR */
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#define DLLGCR_SBIAS BIT(30)
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/* PUBL_DXGCR */
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#define DQSRTT BIT(9)
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#define DQRTT BIT(10)
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/* PIR */
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#define PIR_INIT BIT(0)
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#define PIR_DLLSRST BIT(1)
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#define PIR_DLLLOCK BIT(2)
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#define PIR_ZCAL BIT(3)
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#define PIR_ITMSRST BIT(4)
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#define PIR_DRAMRST BIT(5)
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#define PIR_DRAMINIT BIT(6)
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#define PIR_QSTRN BIT(7)
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#define PIR_RVTRN BIT(8)
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#define PIR_ICPC BIT(16)
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#define PIR_DLLBYP BIT(17)
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#define PIR_CTLDINIT BIT(18)
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#define PIR_CLRSR BIT(28)
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#define PIR_LOCKBYP BIT(29)
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#define PIR_ZCALBYP BIT(30)
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#define PIR_INITBYP BIT(31)
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/* PGCR */
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#define PGCR_DFTLMT_SHIFT 3
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#define PGCR_DFTCMP_SHIFT 2
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#define PGCR_DQSCFG_SHIFT 1
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#define PGCR_ITMDMD_SHIFT 0
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/* PGSR */
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#define PGSR_IDONE BIT(0)
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#define PGSR_DLDONE BIT(1)
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#define PGSR_ZCDONE BIT(2)
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#define PGSR_DIDONE BIT(3)
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#define PGSR_DTDONE BIT(4)
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#define PGSR_DTERR BIT(5)
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#define PGSR_DTIERR BIT(6)
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#define PGSR_DFTERR BIT(7)
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#define PGSR_RVERR BIT(8)
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#define PGSR_RVEIRR BIT(9)
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/* PTR0 */
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#define PRT_ITMSRST_SHIFT 18
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#define PRT_DLLLOCK_SHIFT 6
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#define PRT_DLLSRST_SHIFT 0
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/* PTR1 */
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#define PRT_DINIT0_SHIFT 0
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#define PRT_DINIT1_SHIFT 19
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/* PTR2 */
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#define PRT_DINIT2_SHIFT 0
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#define PRT_DINIT3_SHIFT 17
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/* DCR */
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#define DDRMD_LPDDR 0
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#define DDRMD_DDR 1
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#define DDRMD_DDR2 2
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#define DDRMD_DDR3 3
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#define DDRMD_LPDDR2_LPDDR3 4
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#define DDRMD_MASK 7
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#define DDRMD_SHIFT 0
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#define PDQ_MASK 7
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#define PDQ_SHIFT 4
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/* DXCCR */
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#define DQSNRES_MASK 0xf
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#define DQSNRES_SHIFT 8
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#define DQSRES_MASK 0xf
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#define DQSRES_SHIFT 4
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/* DTPR */
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#define TDQSCKMAX_SHIFT 27
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#define TDQSCKMAX_MASK 7
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#define TDQSCK_SHIFT 24
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#define TDQSCK_MASK 7
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/* DSGCR */
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#define DQSGX_SHIFT 5
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#define DQSGX_MASK 7
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#define DQSGE_SHIFT 8
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#define DQSGE_MASK 7
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/* SCTL */
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#define INIT_STATE 0
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#define CFG_STATE 1
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#define GO_STATE 2
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#define SLEEP_STATE 3
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#define WAKEUP_STATE 4
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/* STAT */
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#define LP_TRIG_SHIFT 4
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#define LP_TRIG_MASK 7
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#define PCTL_STAT_MASK 7
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#define INIT_MEM 0
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#define CONFIG 1
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#define CONFIG_REQ 2
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#define ACCESS 3
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#define ACCESS_REQ 4
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#define LOW_POWER 5
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#define LOW_POWER_ENTRY_REQ 6
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#define LOW_POWER_EXIT_REQ 7
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/* ZQCR*/
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#define PD_OUTPUT_SHIFT 0
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#define PU_OUTPUT_SHIFT 5
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#define PD_ONDIE_SHIFT 10
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#define PU_ONDIE_SHIFT 15
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#define ZDEN_SHIFT 28
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/* DDLGCR */
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#define SBIAS_BYPASS BIT(23)
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/* MCFG */
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#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
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#define PD_IDLE_SHIFT 8
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#define MDDR_EN (2 << 22)
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#define LPDDR2_EN (3 << 22)
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#define LPDDR3_EN (1 << 22)
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#define DDR2_EN (0 << 5)
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#define DDR3_EN (1 << 5)
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#define LPDDR2_S2 (0 << 6)
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#define LPDDR2_S4 (1 << 6)
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#define MDDR_LPDDR2_BL_2 (0 << 20)
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#define MDDR_LPDDR2_BL_4 (1 << 20)
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#define MDDR_LPDDR2_BL_8 (2 << 20)
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#define MDDR_LPDDR2_BL_16 (3 << 20)
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#define DDR2_DDR3_BL_4 0
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#define DDR2_DDR3_BL_8 1
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#define TFAW_SHIFT 18
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#define PD_EXIT_SLOW (0 << 17)
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#define PD_EXIT_FAST (1 << 17)
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#define PD_TYPE_SHIFT 16
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#define BURSTLENGTH_SHIFT 20
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/* POWCTL */
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#define POWER_UP_START BIT(0)
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/* POWSTAT */
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#define POWER_UP_DONE BIT(0)
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/* MCMD */
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enum {
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DESELECT_CMD = 0,
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PREA_CMD,
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REF_CMD,
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MRS_CMD,
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ZQCS_CMD,
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ZQCL_CMD,
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RSTL_CMD,
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MRR_CMD = 8,
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DPDE_CMD,
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};
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#define BANK_ADDR_MASK 7
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#define BANK_ADDR_SHIFT 17
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#define CMD_ADDR_MASK 0x1fff
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#define CMD_ADDR_SHIFT 4
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#define LPDDR23_MA_SHIFT 4
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#define LPDDR23_MA_MASK 0xff
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#define LPDDR23_OP_SHIFT 12
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#define LPDDR23_OP_MASK 0xff
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#define START_CMD (1u << 31)
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/* DDRPHY REG */
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enum {
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/* DDRPHY_REG0 */
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SOFT_RESET_MASK = 3,
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SOFT_DERESET_ANALOG = 1 << 2,
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SOFT_DERESET_DIGITAL = 1 << 3,
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SOFT_RESET_SHIFT = 2,
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/* DDRPHY REG1 */
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PHY_DDR3 = 0,
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PHY_DDR2 = 1,
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PHY_LPDDR3 = 2,
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PHY_LPDDR2 = 3,
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PHT_BL_8 = 1 << 2,
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PHY_BL_4 = 0 << 2,
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/* DDRPHY_REG2 */
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MEMORY_SELECT_DDR3 = 0 << 0,
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MEMORY_SELECT_LPDDR3 = 2 << 0,
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MEMORY_SELECT_LPDDR2 = 3 << 0,
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DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
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DQS_SQU_CAL_SEL_CS1 = 1 << 4,
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DQS_SQU_CAL_SEL_CS0 = 2 << 4,
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DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
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DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
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DQS_SQU_CAL_START = 1 << 0,
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|
DQS_SQU_NO_CAL = 0 << 0,
|
|
};
|
|
|
|
/* CK pull up/down driver strength control */
|
|
enum {
|
|
PHY_RON_RTT_DISABLE = 0,
|
|
PHY_RON_RTT_451OHM = 1,
|
|
PHY_RON_RTT_225OHM,
|
|
PHY_RON_RTT_150OHM,
|
|
PHY_RON_RTT_112OHM,
|
|
PHY_RON_RTT_90OHM,
|
|
PHY_RON_RTT_75OHM,
|
|
PHY_RON_RTT_64OHM = 7,
|
|
|
|
PHY_RON_RTT_56OHM = 16,
|
|
PHY_RON_RTT_50OHM,
|
|
PHY_RON_RTT_45OHM,
|
|
PHY_RON_RTT_41OHM,
|
|
PHY_RON_RTT_37OHM,
|
|
PHY_RON_RTT_34OHM,
|
|
PHY_RON_RTT_33OHM,
|
|
PHY_RON_RTT_30OHM = 23,
|
|
|
|
PHY_RON_RTT_28OHM = 24,
|
|
PHY_RON_RTT_26OHM,
|
|
PHY_RON_RTT_25OHM,
|
|
PHY_RON_RTT_23OHM,
|
|
PHY_RON_RTT_22OHM,
|
|
PHY_RON_RTT_21OHM,
|
|
PHY_RON_RTT_20OHM,
|
|
PHY_RON_RTT_19OHM = 31,
|
|
};
|
|
|
|
/* DQS squelch DLL delay */
|
|
enum {
|
|
DQS_DLL_NO_DELAY = 0,
|
|
DQS_DLL_22P5_DELAY,
|
|
DQS_DLL_45_DELAY,
|
|
DQS_DLL_67P5_DELAY,
|
|
DQS_DLL_90_DELAY,
|
|
DQS_DLL_112P5_DELAY,
|
|
DQS_DLL_135_DELAY,
|
|
DQS_DLL_157P5_DELAY,
|
|
};
|
|
|
|
/* GRF_SOC_CON0 */
|
|
#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
|
|
#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
|
|
#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
|
|
#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
|
|
|
|
#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
|
|
#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
|
|
|
|
#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
|
|
#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
|
|
|
|
#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
|
|
#define DDR3_DLL_RESET (1 << 8)
|
|
|
|
#endif /* _ASM_ARCH_SDRAM_RK322X_H */
|