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![York Sun](/assets/img/avatar_default.png)
Use TARGET_P1025RDB instead of sharing with P1_P2_RDB_PC to simplify Kconfig and config macros. Remove macro CONFIG_P1025RDB. Signed-off-by: York Sun <york.sun@nxp.com>
507 lines
13 KiB
C
507 lines
13 KiB
C
/*
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* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <hwconfig.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_lbc.h>
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#include <asm/mp.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <vsc7385.h>
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#include <ioports.h>
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#include <asm/fsl_serdes.h>
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#include <netdev.h>
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#ifdef CONFIG_QE
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#define GPIO_GETH_SW_PORT 1
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#define GPIO_GETH_SW_PIN 29
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#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
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#define GPIO_SLIC_PORT 1
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#define GPIO_SLIC_PIN 30
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#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
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#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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#define GPIO_DDR_RST_PORT 1
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#define GPIO_DDR_RST_PIN 8
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#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
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#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
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#endif
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#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
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#define PCA_IOPORT_I2C_ADDR 0x23
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#define PCA_IOPORT_OUTPUT_CMD 0x2
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#define PCA_IOPORT_CFG_CMD 0x6
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#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
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#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
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#endif
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GPIO */
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{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
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#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
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#endif
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{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
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{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
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{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
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#ifdef CONFIG_TARGET_P1025RDB
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/* QE_MUX_MDC */
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{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
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/* UCC_1_MII */
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{0, 23, 2, 0, 2}, /* CLK12 */
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{0, 24, 2, 0, 1}, /* CLK9 */
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{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
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{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
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{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
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{0, 17, 2, 0, 2}, /* ENET1_CRS */
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{0, 16, 2, 0, 2}, /* ENET1_COL */
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/* UCC_5_RMII */
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{1, 11, 2, 0, 1}, /* CLK13 */
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{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
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{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
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{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
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{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
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{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
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{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
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{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
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#endif
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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#endif
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struct cpld_data {
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u8 cpld_rev_major;
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u8 pcba_rev;
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u8 wd_cfg;
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u8 rst_bps_sw;
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u8 load_default_n;
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u8 rst_bps_wd;
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u8 bypass_enable;
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u8 bps_led;
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u8 status_led; /* offset: 0x8 */
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u8 fxo_led; /* offset: 0x9 */
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u8 fxs_led; /* offset: 0xa */
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u8 rev4[2];
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u8 system_rst; /* offset: 0xd */
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u8 bps_out;
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u8 rev5[3];
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u8 cpld_rev_minor;
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};
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#define CPLD_WD_CFG 0x03
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#define CPLD_RST_BSW 0x00
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#define CPLD_RST_BWD 0x00
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#define CPLD_BYPASS_EN 0x03
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#define CPLD_STATUS_LED 0x01
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#define CPLD_FXO_LED 0x01
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#define CPLD_FXS_LED 0x0F
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#define CPLD_SYS_RST 0x00
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void board_cpld_init(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
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out_8(&cpld_data->status_led, CPLD_STATUS_LED);
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out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
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out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
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out_8(&cpld_data->system_rst, CPLD_SYS_RST);
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}
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void board_gpio_init(void)
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{
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#ifdef CONFIG_QE
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
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#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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/* reset DDR3 */
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setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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udelay(1000);
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clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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udelay(1000);
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setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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/* disable CE_PB8 */
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clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
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#endif
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/* Enable VSC7385 switch */
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setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
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/* Enable SLIC */
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setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
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#else
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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/*
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* GPIO10 DDR Reset, open drain
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* GPIO7 LOAD_DEFAULT_N Input
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* GPIO11 WDI (watchdog input)
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* GPIO12 Ethernet Switch Reset
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* GPIO13 SLIC Reset
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*/
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setbits_be32(&pgpio->gpdir, 0x02130000);
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#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
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/* init DDR3 reset signal */
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setbits_be32(&pgpio->gpdir, 0x00200000);
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setbits_be32(&pgpio->gpodr, 0x00200000);
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clrbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(1000);
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setbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(1000);
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clrbits_be32(&pgpio->gpdir, 0x00200000);
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#endif
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#ifdef CONFIG_VSC7385_ENET
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/* reset VSC7385 Switch */
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setbits_be32(&pgpio->gpdir, 0x00080000);
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setbits_be32(&pgpio->gpdat, 0x00080000);
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#endif
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#ifdef CONFIG_SLIC
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/* reset SLIC */
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setbits_be32(&pgpio->gpdir, 0x00040000);
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setbits_be32(&pgpio->gpdat, 0x00040000);
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#endif
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#endif
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}
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
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clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
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clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
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board_gpio_init();
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board_cpld_init();
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return 0;
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}
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int checkboard(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u8 in, out, io_config, val;
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printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
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in_8(&cpld_data->cpld_rev_major) & 0x0F,
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in_8(&cpld_data->cpld_rev_minor) & 0x0F,
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in_8(&cpld_data->pcba_rev) & 0x0F);
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/* Initialize i2c early for rom_loc and flash bank information */
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i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
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if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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val = (in & io_config) | (out & (~io_config));
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puts("rom_loc: ");
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if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
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puts("sd");
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#ifdef __SW_BOOT_SPI
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} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
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puts("spi");
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#endif
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#ifdef __SW_BOOT_NAND
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} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
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puts("nand");
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#endif
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#ifdef __SW_BOOT_PCIE
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} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
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puts("pcie");
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#endif
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} else {
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if (val & 0x2)
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puts("nor lower bank");
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else
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puts("nor upper bank");
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}
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puts("\n");
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if (val & 0x1) {
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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puts("SD/MMC : 8-bit Mode\n");
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puts("eSPI : Disabled\n");
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} else {
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puts("SD/MMC : 4-bit Mode\n");
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puts("eSPI : Enabled\n");
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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ccsr_gur_t *gur __attribute__((unused)) =
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(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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#ifdef CONFIG_VSC7385_ENET
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char *tmp;
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unsigned int vscfw_addr;
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#endif
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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printf("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_VSC7385_ENET
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/* If a VSC7385 microcode image is present, then upload it. */
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if ((tmp = getenv("vscfw_addr")) != NULL) {
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vscfw_addr = simple_strtoul(tmp, NULL, 16);
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printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
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if (vsc7385_upload_firmware((void *) vscfw_addr,
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CONFIG_VSC7385_IMAGE_SIZE))
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puts("Failure uploading VSC7385 microcode.\n");
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} else
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puts("No address specified for VSC7385 microcode.\n");
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#endif
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mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#if defined(CONFIG_UEC_ETH)
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/* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
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uec_standard_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_QE) && \
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(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
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static void fdt_board_fixup_qe_pins(void *blob)
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{
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unsigned int oldbus;
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u8 val8;
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int node;
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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if (hwconfig("qe")) {
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/* For QE and eLBC pins multiplexing,
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* there is a PCA9555 device on P1025RDB.
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* It control the multiplex pins' functions,
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* and setting the PCA9555 can switch the
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* function between QE and eLBC.
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*/
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oldbus = i2c_get_bus_num();
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i2c_set_bus_num(0);
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if (hwconfig("tdm"))
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val8 = PCA_IOPORT_QE_TDM_ENABLE;
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else
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val8 = PCA_IOPORT_QE_PIN_ENABLE;
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i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
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1, &val8, 1);
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i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
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1, &val8, 1);
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i2c_set_bus_num(oldbus);
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/* if run QE TDM, Set ABSWP to implement
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* conversion of addresses in the eLBC.
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*/
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if (hwconfig("tdm")) {
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set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
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set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
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setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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}
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} else {
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node = fdt_path_offset(blob, "/qe");
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if (node >= 0)
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fdt_del_node(blob, node);
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}
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return;
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
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const char *soc_usb_compat = "fsl-usb2-dr";
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int usb_err, usb1_off, usb2_off;
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#endif
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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int err;
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#endif
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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FT_FSL_PCI_SETUP;
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#ifdef CONFIG_QE
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do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
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sizeof("okay"), 0);
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#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
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fdt_board_fixup_qe_pins(blob);
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#endif
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#endif
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#if defined(CONFIG_HAS_FSL_DR_USB)
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fsl_fdt_fixup_dr_usb(blob, bd);
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#endif
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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/* Delete eLBC node as it is muxed with USB2 controller */
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if (hwconfig("usb2")) {
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const char *soc_elbc_compat = "fsl,p1020-elbc";
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int off = fdt_node_offset_by_compatible(blob, -1,
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soc_elbc_compat);
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if (off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_elbc_compat);
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return off;
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}
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err = fdt_del_node(blob, off);
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if (err < 0) {
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printf("WARNING: could not remove %s\n",
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soc_elbc_compat);
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return err;
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
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/* Delete USB2 node as it is muxed with eLBC */
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usb1_off = fdt_node_offset_by_compatible(blob, -1,
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soc_usb_compat);
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if (usb1_off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_usb_compat);
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return usb1_off;
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}
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usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
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soc_usb_compat);
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if (usb2_off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_usb_compat);
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return usb2_off;
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}
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usb_err = fdt_del_node(blob, usb2_off);
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if (usb_err < 0) {
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printf("WARNING: could not remove %s\n", soc_usb_compat);
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return usb_err;
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}
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#endif
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return 0;
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}
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#endif
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