mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
86 lines
3.2 KiB
C
86 lines
3.2 KiB
C
/*
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* MCF5282 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5282__
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#define __IMMAP_5282__
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struct sys_ctrl {
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uint ipsbar;
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char res1[4];
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uint rambar;
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char res2[4];
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uchar crsr;
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uchar cwcr;
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uchar lpicr;
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uchar cwsr;
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uint dmareqc;
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char res3[4];
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uint mpark;
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/* TODO: finish these */
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};
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/* Fast ethernet controller registers
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*/
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typedef struct fec {
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uint res1; /* reserved 1000*/
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uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
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uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
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uint res2; /* reserved 100c*/
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uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
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uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
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uint res3[3]; /* reserved 1018*/
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uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
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uint res4[6]; /* reserved 1028*/
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uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
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uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
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/*1044*/
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uint res5[7]; /* reserved 1048*/
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uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
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uint res6[7]; /* reserved 1068*/
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uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
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uint res7[15]; /* reserved 1088*/
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uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
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uint res8[7]; /* reserved 10C8*/
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uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
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uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
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uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
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uint res9[10]; /* reserved 10F0*/
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uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
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uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
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uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
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uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
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uint res10[7]; /* reserved 1128*/
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uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
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uint res11; /* reserved 1148*/
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uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
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uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
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uint res12[11]; /* reserved 1154*/
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uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
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uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
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uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
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} fec_t;
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#endif /* __IMMAP_5282__ */
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