Stephen Warren a4bcd67c72 ARM: tegra: remove a conditional for CSITE rate ... There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2014-02-03 09:46:46 -07:00
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tegra20	arm720t: convert makefiles to Kbuild style	2013-10-31 12:53:39 -04:00
tegra30	ARM: tegra: don't exceed AVP limits when configuring PLLP	2014-02-03 09:46:45 -07:00
tegra114	ARM: tegra: pass just partition ID to power_partition()	2014-02-03 09:46:46 -07:00
tegra-common	ARM: tegra: remove a conditional for CSITE rate	2014-02-03 09:46:46 -07:00
config.mk	ARM: merge commonly-defined PLATFORM_RELFLAGS	2014-01-24 16:59:08 -05:00
cpu.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
interrupts.c	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
Makefile	ARM: tegra: move Tegra specific code under arch/arm/	2013-10-31 13:26:44 -04:00
start.S	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00