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7c75f7f1b2
In preparation to add support for the Dragonboard820c (APQ8096), refactor the current Snapdragon clock driver. No new functionality has been added. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Qualcomm APQ8916 sysmap
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MACH_SYSMAP_APQ8016_H
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#define _MACH_SYSMAP_APQ8016_H
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#define GICD_BASE (0x0b000000)
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#define GICC_BASE (0x0a20c000)
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x2101C)
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#define APCS_GPLL_ENA_VOTE (0x45000)
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#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
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#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
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#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
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#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
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#define SDCC_N(n) ((n * 0x1000) + 0x41010)
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#define SDCC_D(n) ((n * 0x1000) + 0x41014)
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#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
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#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
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/* BLSP1 AHB clock (root clock for BLSP) */
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#define BLSP1_AHB_CBCR 0x1008
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/* Uart clock control registers */
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#define BLSP1_UART2_BCR (0x3028)
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#define BLSP1_UART2_APPS_CBCR (0x302C)
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#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
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#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
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#define BLSP1_UART2_APPS_M (0x303C)
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#define BLSP1_UART2_APPS_N (0x3040)
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#define BLSP1_UART2_APPS_D (0x3044)
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#endif
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