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9955b4ab01
u-boot-brain/arch/arm/include/asm/arch-fsl-lsch3
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York Sun 9955b4ab01 driver/ddr/fsl: Add workaround for A008336 
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:06 -08:00
..
clock.h ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
config.h driver/ddr/fsl: Add workaround for A008336 2015-02-24 13:09:06 -08:00
gpio.h ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
immap_lsch3.h armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
imx-regs.h ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00