mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
9a0e21a3a8
(0xf5000000, to be specific). The reason is that the RTC first gets accessed before MMU is initialized and, consequently, it needs to be placed at physical addresses which are later mapped to the same virtual addresses (like 0xf5000000 physical is mapped to 0xf5000000 virtual).
509 lines
16 KiB
C
509 lines
16 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_ATC 1 /* ...on a ATC board */
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else*/
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#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
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#define CONFIG_BAUDRATE 115200
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_ON_FCC
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#define CONFIG_NET_MULTI
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#define CONFIG_ETHER_ON_FCC2
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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#define CONFIG_ETHER_ON_FCC3
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/*
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* - Rx-CLK is CLK15
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* - Tx-CLK is CLK16
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* - RAM for BD/Buffers is on the local Bus (see 28-13)
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* - Enable Half Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
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# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 64000000 /* in Hz */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
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#define CONFIG_PREBOOT \
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"echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
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"bootm"
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/*-----------------------------------------------------------------------
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* Miscellaneous configuration options
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_EEPROM | \
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CFG_CMD_PCI | \
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CFG_CMD_PCMCIA | \
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CFG_CMD_DATE | \
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CFG_CMD_IDE)
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#define CONFIG_DOS_PARTITION
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
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#define CFG_ALLOC_DPRAM
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SPI
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#define CONFIG_RTC_DS12887
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#define RTC_BASE_ADDR 0xF5000000
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#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
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#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
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#define CONFIG_MISC_INIT_R
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Flash configuration
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*/
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#define CFG_FLASH_BASE 0xFF000000
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#define CFG_FLASH_SIZE 0x00800000
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CONFIG_FLASH_16BIT
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* if you change bits in the HRCW, you must also change the CFG_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
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*/
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#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
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HRCW_BPS10 |\
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HRCW_APPC10)
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/* no slaves so just fill with zeros */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*
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* 60x SDRAM is mapped at CFG_SDRAM_BASE.
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
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#if 1
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/* environment is in Flash */
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#define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000)
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# define CFG_ENV_SIZE 0x10000
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# define CFG_ENV_SECT_SIZE 0x10000
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#else
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0
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#define CFG_ENV_SIZE 2048
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
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HID0_DCI|HID0_IFEM|HID0_ABE)
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#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CFG_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define BCR_APD01 0x10000000
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#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
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SIUMCR_CS10PC00|SIUMCR_BCTLC10)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CFG_SCCR SCCR_DFBRG01
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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#define CFG_MIN_AM_MASK 0xC0000000
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/*-----------------------------------------------------------------------
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* MPTPR - Memory Refresh Timer Prescaler Register 10-18
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*-----------------------------------------------------------------------
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*/
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#define CFG_MPTPR 0x1F00
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/*-----------------------------------------------------------------------
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* PSRT - Refresh Timer Register 10-16
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*-----------------------------------------------------------------------
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*/
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#define CFG_PSRT 0x0f
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/*-----------------------------------------------------------------------
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* PSRT - SDRAM Mode Register 10-10
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*-----------------------------------------------------------------------
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*/
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/* SDRAM initialization values for 8-column chips
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*/
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#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI1_A7 |\
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ORxS_NUMR_12)
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#define CFG_PSDMR_8COL (PSDMR_PBI |\
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PSDMR_SDAM_A15_IS_A5 |\
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PSDMR_BSMA_A15_A17 |\
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PSDMR_SDA10_PBI1_A7 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_3W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* SDRAM initialization values for 9-column chips
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*/
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#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI1_A6 |\
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ORxS_NUMR_12)
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#define CFG_PSDMR_9COL (PSDMR_PBI |\
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PSDMR_SDAM_A16_IS_A5 |\
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PSDMR_BSMA_A15_A17 |\
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PSDMR_SDA10_PBI1_A6 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_3W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit Boot ROM
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* 1 60x GPCM 64 bit FLASH
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* 2 60x SDRAM 64 bit SDRAM
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*
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*/
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#define CFG_MRS_OFFS 0x00000000
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/* Bank 0 - FLASH
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*/
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_16 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_3_CLK |\
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ORxU_EHTR_8IDLE)
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/* Bank 2 - 60x bus SDRAM
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CFG_OR2_PRELIM CFG_OR2_8COL
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#define CFG_PSDMR CFG_PSDMR_8COL
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#endif /* CFG_RAMBOOT */
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#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_UPMA |\
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BRx_V)
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#define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_I82365
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#define CFG_PCMCIA_MEM_ADDR 0x81000000
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#define CFG_PCMCIA_MEM_SIZE 0x1000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR 0xa0000000
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET 0x100
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET 0x100
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x108
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#endif /* __CONFIG_H */
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