mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
566ce04de4
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
233 lines
6.2 KiB
ArmAsm
233 lines
6.2 KiB
ArmAsm
/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <config.h>
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#include <gt64120.h>
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#include <msc01.h>
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#include <pci.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/malta.h>
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#include <asm/mipsregs.h>
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#ifdef CONFIG_SYS_BIG_ENDIAN
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#define CPU_TO_GT32(_x) ((_x))
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#else
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#define CPU_TO_GT32(_x) ( \
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(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
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(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
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#endif
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.text
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.set noreorder
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.globl lowlevel_init
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lowlevel_init:
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/* detect the core card */
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PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
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lw t0, 0(t0)
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srl t0, t0, MALTA_REVISION_CORID_SHF
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andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
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MALTA_REVISION_CORID_SHF)
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/* core cards using the gt64120 system controller */
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li t1, MALTA_REVISION_CORID_CORE_LV
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beq t0, t1, _gt64120
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/* core cards using the MSC01 system controller */
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li t1, MALTA_REVISION_CORID_CORE_FPGA6
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beq t0, t1, _msc01
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nop
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/* unknown system controller */
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b .
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nop
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/*
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* Load BAR registers of GT64120 as done by YAMON
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*
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* based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
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* to the barebox mailing list.
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* The subject of the original patch:
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* 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
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* URL:
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* http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
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*
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* based on write_bootloader() in qemu.git/hw/mips_malta.c
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* see GT64120 manual and qemu.git/hw/gt64xxx.c for details
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*/
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_gt64120:
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
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li t0, CPU_TO_GT32(0xdf000000)
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sw t0, GT_ISD_OFS(t1)
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/* setup MEM-to-PCI0 mapping */
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PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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li t0, CPU_TO_GT32(0xc0000000)
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sw t0, GT_PCI0IOLD_OFS(t1)
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li t0, CPU_TO_GT32(0x40000000)
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sw t0, GT_PCI0IOHD_OFS(t1)
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/* setup PCI0 mem windows */
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li t0, CPU_TO_GT32(0x80000000)
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sw t0, GT_PCI0M0LD_OFS(t1)
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li t0, CPU_TO_GT32(0x3f000000)
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sw t0, GT_PCI0M0HD_OFS(t1)
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li t0, CPU_TO_GT32(0xc1000000)
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sw t0, GT_PCI0M1LD_OFS(t1)
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li t0, CPU_TO_GT32(0x5e000000)
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sw t0, GT_PCI0M1HD_OFS(t1)
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jr ra
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nop
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/*
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*
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*/
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_msc01:
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/* setup peripheral bus controller clock divide */
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PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
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li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
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sw t1, MSC01_PBC_CLKCFG_OFS(t0)
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/* tweak peripheral bus controller timings */
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li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
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(0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
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sw t1, MSC01_PBC_CS0TIM_OFS(t0)
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li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
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(0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
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(0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
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(0x2 << MSC01_PBC_CS0RW_WAT_SHF)
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sw t1, MSC01_PBC_CS0RW_OFS(t0)
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lw t1, MSC01_PBC_CS0CFG_OFS(t0)
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li t2, MSC01_PBC_CS0CFG_DTYP_MSK
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and t1, t2
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ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
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(0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
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(0x10 << MSC01_PBC_CS0CFG_WS_SHF)
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sw t1, MSC01_PBC_CS0CFG_OFS(t0)
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/* setup basic address decode */
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PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
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li t1, 0x0
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li t2, -CONFIG_SYS_MEM_SIZE
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sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
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sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
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sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
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sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
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/* initialise IP1 - unused */
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li t1, MALTA_MSC01_IP1_BASE
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li t2, -MALTA_MSC01_IP1_SIZE
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sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
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sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
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sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
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sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
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/* initialise IP2 - PCI */
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li t1, MALTA_MSC01_IP2_BASE1
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li t2, -MALTA_MSC01_IP2_SIZE1
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sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
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sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
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li t1, MALTA_MSC01_IP2_BASE2
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li t2, -MALTA_MSC01_IP2_SIZE2
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sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
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sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
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/* initialise IP3 - peripheral bus controller */
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li t1, MALTA_MSC01_IP3_BASE
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li t2, -MALTA_MSC01_IP3_SIZE
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sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
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sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
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sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
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sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
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/* setup PCI memory */
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PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
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li t1, MALTA_MSC01_PCIMEM_BASE
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li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
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li t3, MALTA_MSC01_PCIMEM_MAP
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sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
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sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
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sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
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/* setup PCI I/O */
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li t1, MALTA_MSC01_PCIIO_BASE
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li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
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li t3, MALTA_MSC01_PCIIO_MAP
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sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
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sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
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sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
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/* setup PCI_BAR0 memory window */
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li t1, -CONFIG_SYS_MEM_SIZE
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sw t1, MSC01_PCI_BAR0_OFS(t0)
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/* setup PCI to SysCon/CPU translation */
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sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
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sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
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/* setup PCI vendor & device IDs */
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li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
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(PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
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sw t1, MSC01_PCI_HEAD0_OFS(t0)
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/* setup PCI subsystem vendor & device IDs */
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sw t1, MSC01_PCI_HEAD11_OFS(t0)
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/* setup PCI class, revision */
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li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
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(0x1 << MSC01_PCI_HEAD2_REV_SHF)
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sw t1, MSC01_PCI_HEAD2_OFS(t0)
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/* ensure a sane setup */
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sw zero, MSC01_PCI_HEAD3_OFS(t0)
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sw zero, MSC01_PCI_HEAD4_OFS(t0)
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sw zero, MSC01_PCI_HEAD5_OFS(t0)
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sw zero, MSC01_PCI_HEAD6_OFS(t0)
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sw zero, MSC01_PCI_HEAD7_OFS(t0)
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sw zero, MSC01_PCI_HEAD8_OFS(t0)
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sw zero, MSC01_PCI_HEAD9_OFS(t0)
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sw zero, MSC01_PCI_HEAD10_OFS(t0)
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sw zero, MSC01_PCI_HEAD12_OFS(t0)
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sw zero, MSC01_PCI_HEAD13_OFS(t0)
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sw zero, MSC01_PCI_HEAD14_OFS(t0)
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sw zero, MSC01_PCI_HEAD15_OFS(t0)
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/* setup PCI command register */
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li t1, (PCI_COMMAND_FAST_BACK | \
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PCI_COMMAND_SERR | \
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PCI_COMMAND_PARITY | \
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PCI_COMMAND_MASTER | \
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PCI_COMMAND_MEMORY)
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sw t1, MSC01_PCI_HEAD1_OFS(t0)
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/* setup PCI byte swapping */
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#ifdef CONFIG_SYS_BIG_ENDIAN
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li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
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(0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
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sw t1, MSC01_PCI_SWAP_OFS(t0)
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#else
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sw zero, MSC01_PCI_SWAP_OFS(t0)
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#endif
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/* enable PCI host configuration cycles */
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lw t1, MSC01_PCI_CFG_OFS(t0)
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li t2, MSC01_PCI_CFG_RA_MSK | \
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MSC01_PCI_CFG_G_MSK | \
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MSC01_PCI_CFG_EN_MSK
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or t1, t1, t2
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sw t1, MSC01_PCI_CFG_OFS(t0)
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jr ra
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nop
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