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https://github.com/brain-hackers/u-boot-brain
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98ef128b56
The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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* Ryan Chen <ryan_chen@aspeedtech.com>
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*
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* Copyright 2016 IBM Corporation
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* (C) Copyright 2016 Google, Inc
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*/
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#ifndef _ASPEED_COMMON_CONFIG_H
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#define _ASPEED_COMMON_CONFIG_H
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#include <asm/arch/platform.h>
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/* Misc CPU related */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
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#ifdef CONFIG_PRE_CON_BUF_SZ
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#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
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#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
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#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
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#endif
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#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
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+ CONFIG_SYS_INIT_RAM_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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/*
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* NS16550 Configuration
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*/
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=yes\0" \
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"spi_dma=yes\0" \
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""
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#endif /* __AST_COMMON_CONFIG_H */
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