mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
![Sanchayan Maity](/assets/img/avatar_default.png)
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
7 lines
163 B
Plaintext
7 lines
163 B
Plaintext
Colibri VFxx
|
|
M: Stefan Agner <stefan.agner@toradex.com>
|
|
S: Maintained
|
|
F: board/toradex/colibri_vf/
|
|
F: include/configs/colibri_vf.h
|
|
F: configs/colibri_vf_defconfig
|