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![Simon Glass](/assets/img/avatar_default.png)
This is a network function so let's move it into that header. Signed-off-by: Simon Glass <sjg@chromium.org>
212 lines
5.1 KiB
C
212 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <exports.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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DECLARE_GLOBAL_DATA_PTR;
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static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
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{
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int phy_reg;
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u32 phy_id;
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
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phy_id = (phy_reg & 0xffff) << 16;
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
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phy_id |= (phy_reg & 0xffff);
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if (phy_id == PHY_UID_IN112525_S03)
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return true;
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else
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return false;
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FSL_MC_ENET)
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struct memac_mdio_info mdio_info;
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struct memac_mdio_controller *reg;
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int i, interface;
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struct mii_dev *dev;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
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/* Register the EMI 1 */
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fm_memac_mdio_init(bis, &mdio_info);
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
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/* Register the EMI 2 */
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fm_memac_mdio_init(bis, &mdio_info);
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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switch (srds_s1) {
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case 19:
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wriop_set_phy_address(WRIOP1_DPMAC2, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC3, 0,
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AQR107_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC4, 0,
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AQR107_PHY_ADDR2);
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if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
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wriop_set_phy_address(WRIOP1_DPMAC5, 0,
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INPHI_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC6, 0,
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INPHI_PHY_ADDR1);
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}
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wriop_set_phy_address(WRIOP1_DPMAC17, 0,
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RGMII_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC18, 0,
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RGMII_PHY_ADDR2);
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break;
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case 18:
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wriop_set_phy_address(WRIOP1_DPMAC7, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC8, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC9, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC10, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC3, 0,
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AQR107_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC4, 0,
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AQR107_PHY_ADDR2);
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if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
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wriop_set_phy_address(WRIOP1_DPMAC5, 0,
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INPHI_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC6, 0,
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INPHI_PHY_ADDR1);
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}
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wriop_set_phy_address(WRIOP1_DPMAC17, 0,
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RGMII_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC18, 0,
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RGMII_PHY_ADDR2);
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break;
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default:
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printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
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srds_s1);
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goto next;
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}
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for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
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interface = wriop_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
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wriop_set_mdio(i, dev);
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break;
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case PHY_INTERFACE_MODE_25G_AUI:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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wriop_set_mdio(i, dev);
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break;
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case PHY_INTERFACE_MODE_XLAUI:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
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wriop_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
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interface = wriop_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
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wriop_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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next:
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cpu_eth_init(bis);
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#endif /* CONFIG_FSL_MC_ENET */
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#ifdef CONFIG_PHY_AQUANTIA
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/*
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* Export functions to be used by AQ firmware
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* upload application
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*/
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gd->jt->strcpy = strcpy;
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gd->jt->mdelay = mdelay;
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gd->jt->mdio_get_current_dev = mdio_get_current_dev;
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gd->jt->phy_find_by_mask = phy_find_by_mask;
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gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
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gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_RESET_PHY_R)
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void reset_phy(void)
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{
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#if defined(CONFIG_FSL_MC_ENET)
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mc_env_boot();
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#endif
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}
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#endif /* CONFIG_RESET_PHY_R */
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int fdt_fixup_board_phy(void *fdt)
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{
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int mdio_offset;
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int ret;
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struct mii_dev *dev;
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ret = 0;
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
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mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
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if (mdio_offset < 0)
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mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
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if (mdio_offset < 0) {
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printf("mdio@0x8B9700 node not found in dts\n");
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return mdio_offset;
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}
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ret = fdt_setprop_string(fdt, mdio_offset, "status",
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"disabled");
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if (ret) {
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printf("Could not set disable mdio@0x8B97000 %s\n",
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fdt_strerror(ret));
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return ret;
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}
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}
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return ret;
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}
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