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https://github.com/brain-hackers/u-boot-brain
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5c740711f0
Include config.h earlier in the set of #includes so as to avoid a incidental and duplicate definition of CFG_CACHELINE_SIZE. Signed-off-by: Jon Loeliger
148 lines
3.3 KiB
ArmAsm
148 lines
3.3 KiB
ArmAsm
/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCIE1 0x00200000
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#define LAWAR_TRGT_PCIE2 0x00100000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#else
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#define LAWBAR1 0
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#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
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#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0
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addi r5,r7,0
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/* Skip LAWAR0, start at LAWAR1 */
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4)
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5)
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/* LAWBAR2, LAWAR2 */
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5)
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/* LAWBAR3, LAWAR3 */
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5)
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/* LAWBAR4, LAWAR4 */
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5)
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/* LAWBAR5, LAWAR5 */
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5)
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/* LAWBAR6, LAWAR6 */
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5)
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/* LAWBAR7, LAWAR7 */
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5)
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/* LAWBAR8, LAWAR8 */
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lis r6,LAWBAR8@h
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ori r6,r6,LAWBAR8@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR8@h
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ori r6,r6,LAWAR8@l
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stwu r6, 0x20(r5)
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/* LAWBAR9, LAWAR9 */
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lis r6,LAWBAR9@h
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ori r6,r6,LAWBAR9@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR9@h
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ori r6,r6,LAWAR9@l
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stwu r6, 0x20(r5)
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