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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
354 lines
10 KiB
C
354 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Texas Instruments da8xx "glue layer"
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*
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* Copyright (c) 2019, by Texas Instruments
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*
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* Based on the DA8xx "glue layer" code.
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* Copyright (c) 2008-2019, MontaVista Software, Inc. <source@mvista.com>
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*
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* DT support
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* Copyright (c) 2016 Petr Kulhavy <petr@barix.com>
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* This file is part of the Inventra Controller Driver for Linux.
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/device-internal.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/da8xx-usb.h>
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#include <linux/delay.h>
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#include <linux/usb/otg.h>
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#include <asm/omap_musb.h>
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#include <generic-phy.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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#include "musb_uboot.h"
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/* USB 2.0 OTG module registers */
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#define DA8XX_USB_REVISION_REG 0x00
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#define DA8XX_USB_CTRL_REG 0x04
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#define DA8XX_USB_STAT_REG 0x08
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#define DA8XX_USB_EMULATION_REG 0x0c
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#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
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#define DA8XX_USB_INTR_SRC_REG 0x20
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#define DA8XX_USB_INTR_SRC_SET_REG 0x24
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#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
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#define DA8XX_USB_INTR_MASK_REG 0x2c
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#define DA8XX_USB_INTR_MASK_SET_REG 0x30
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#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
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#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
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#define DA8XX_USB_END_OF_INTR_REG 0x3c
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#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
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/* Control register bits */
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#define DA8XX_SOFT_RESET_MASK 1
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#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
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#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
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/* USB interrupt register bits */
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#define DA8XX_INTR_USB_SHIFT 16
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#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
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/* interrupts and DRVVBUS interrupt */
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#define DA8XX_INTR_DRVVBUS 0x100
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#define DA8XX_INTR_RX_SHIFT 8
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#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
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#define DA8XX_INTR_TX_SHIFT 0
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#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
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#define DA8XX_MENTOR_CORE_OFFSET 0x400
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static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 status;
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spin_lock_irqsave(&musb->lock, flags);
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/*
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* NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
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* the Mentor registers (except for setup), use the TI ones and EOI.
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*/
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/* Acknowledge and handle non-CPPI interrupts */
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status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
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if (!status)
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goto eoi;
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
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dev_dbg(musb->controller, "USB IRQ %08x\n", status);
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musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
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musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
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musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
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/*
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* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
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* DA8xx's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.Session per Mentor docs requires that we know its
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* value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
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* Also, DRVVBUS pulses for SRP (but not at 5 V)...
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*/
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if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
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int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
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void __iomem *mregs = musb->mregs;
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err;
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err = musb->int_usb & MUSB_INTR_VBUSERROR;
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if (err) {
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/*
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* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"-starting sessions
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* without waiting for VBUS to stop registering in
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* devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (drvvbus) {
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MUSB_HST_MODE(musb);
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musb->port1_status |= USB_PORT_STAT_POWER;
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} else if (!(musb->int_usb & MUSB_INTR_BABBLE)) {
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/*
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* When babble condition happens, drvvbus interrupt
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* is also generated. Ignore this drvvbus interrupt
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* and let babble interrupt handler recovers the
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* controller; otherwise, the host-mode flag is lost
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* due to the MUSB_DEV_MODE() call below and babble
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* recovery logic will not be called.
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*/
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
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musb->port1_status &= ~USB_PORT_STAT_POWER;
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}
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ret = IRQ_HANDLED;
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}
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if (musb->int_tx || musb->int_rx || musb->int_usb)
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ret |= musb_interrupt(musb);
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eoi:
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/* EOI needs to be written for the IRQ to be re-asserted. */
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if (ret == IRQ_HANDLED || status)
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musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
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spin_unlock_irqrestore(&musb->lock, flags);
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return ret;
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}
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static int da8xx_musb_init(struct musb *musb)
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{
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u32 revision;
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void __iomem *reg_base = musb->ctrl_base;
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int ret;
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/* reset the controller */
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writel(0x1, &da8xx_usb_regs->control);
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udelay(50);
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/* Returns zero if e.g. not clocked */
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revision = readl(&da8xx_usb_regs->revision);
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if (revision == 0)
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return -ENODEV;
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/* Disable all interrupts */
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writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
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DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
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musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
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/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
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debug("DA8xx OTG revision %08x, control %02x\n", revision,
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musb_readb(reg_base, DA8XX_USB_CTRL_REG));
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musb->isr = da8xx_musb_interrupt;
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return 0;
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}
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static int da8xx_musb_exit(struct musb *musb)
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{
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/* flush any interrupts */
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writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
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DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
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writel(0, &da8xx_usb_regs->eoi);
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return 0;
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}
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/**
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* da8xx_musb_enable - enable interrupts
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*/
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static int da8xx_musb_enable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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u32 mask;
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/* Workaround: setup IRQs through both register sets. */
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mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
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((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
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DA8XX_INTR_USB_MASK;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
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DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
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return 0;
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}
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/**
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* da8xx_musb_disable - disable HDRC and flush interrupts
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*/
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static void da8xx_musb_disable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
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DA8XX_INTR_USB_MASK |
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DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
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musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
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}
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void da8xx_musb_reset(struct udevice *dev)
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{
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void *reg_base = dev_read_addr_ptr(dev);
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/* Reset the controller */
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musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
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}
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void da8xx_musb_clear_irq(struct udevice *dev)
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{
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/* flush any interrupts */
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writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
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DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
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writel(0, &da8xx_usb_regs->eoi);
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}
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const struct musb_platform_ops da8xx_ops = {
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.init = da8xx_musb_init,
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.exit = da8xx_musb_exit,
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.enable = da8xx_musb_enable,
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.disable = da8xx_musb_disable,
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};
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struct da8xx_musb_platdata {
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void *base;
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void *ctrl_mod_base;
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struct musb_hdrc_platform_data plat;
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struct musb_hdrc_config musb_config;
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struct omap_musb_board_data otg_board_data;
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struct phy phy;
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};
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static int da8xx_musb_ofdata_to_platdata(struct udevice *dev)
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{
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struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(dev);
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platdata->base = (void *)dev_read_addr_ptr(dev);
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platdata->musb_config.multipoint = 1;
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platdata->musb_config.dyn_fifo = 1;
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platdata->musb_config.num_eps = 5;
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platdata->musb_config.ram_bits = 10;
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platdata->plat.power = fdtdec_get_int(fdt, node, "power", 50);
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platdata->otg_board_data.interface_type = MUSB_INTERFACE_UTMI;
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platdata->plat.mode = MUSB_HOST;
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platdata->otg_board_data.dev = dev;
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platdata->plat.config = &platdata->musb_config;
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platdata->plat.platform_ops = &da8xx_ops;
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platdata->plat.board_data = &platdata->otg_board_data;
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platdata->otg_board_data.clear_irq = da8xx_musb_clear_irq;
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platdata->otg_board_data.reset = da8xx_musb_reset;
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return 0;
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}
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static int da8xx_musb_probe(struct udevice *dev)
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{
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struct musb_host_data *host = dev_get_priv(dev);
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struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
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struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
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struct omap_musb_board_data *otg_board_data;
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int ret;
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void *base = dev_read_addr_ptr(dev);
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/* Get the phy info from the device tree */
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ret = generic_phy_get_by_name(dev, "usb-phy", &platdata->phy);
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if (ret)
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return ret;
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/* Initialize the phy */
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ret = generic_phy_init(&platdata->phy);
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if (ret)
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return ret;
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/* enable psc for usb2.0 */
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lpsc_on(33);
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/* Enable phy */
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generic_phy_power_on(&platdata->phy);
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priv->desc_before_addr = true;
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otg_board_data = &platdata->otg_board_data;
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host->host = musb_init_controller(&platdata->plat,
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(struct device *)otg_board_data,
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platdata->base);
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if (!host->host) {
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ret = -ENODEV;
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goto shutdown; /* Shutdown what we started */
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}
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ret = musb_lowlevel_init(host);
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if (ret == 0)
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return 0;
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shutdown:
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/* Turn off the phy if we fail */
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generic_phy_power_off(&platdata->phy);
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lpsc_disable(33);
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return ret;
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}
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static int da8xx_musb_remove(struct udevice *dev)
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{
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struct musb_host_data *host = dev_get_priv(dev);
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musb_stop(host->host);
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return 0;
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}
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static const struct udevice_id da8xx_musb_ids[] = {
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{ .compatible = "ti,da830-musb" },
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{ }
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};
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U_BOOT_DRIVER(da8xx_musb) = {
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.name = "da8xx-musb",
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.id = UCLASS_USB,
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.of_match = da8xx_musb_ids,
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.ofdata_to_platdata = da8xx_musb_ofdata_to_platdata,
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.probe = da8xx_musb_probe,
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.remove = da8xx_musb_remove,
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.ops = &musb_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct da8xx_musb_platdata),
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.priv_auto_alloc_size = sizeof(struct musb_host_data),
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};
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