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![Graeme Russ](/assets/img/avatar_default.png)
In some circumstances, reset_timer_masked() was called be timer_init() in order to perform architecture specific timer initialisation. In such cases, the required code in reset_timer_masked() has been moved into timer_init()
199 lines
4.9 KiB
C
199 lines
4.9 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/pantheon.h>
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/*
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* Timer registers
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* Refer 6.2.9 in Datasheet
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*/
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struct panthtmr_registers {
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u32 clk_ctrl; /* Timer clk control reg */
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u32 match[9]; /* Timer match registers */
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u32 count[3]; /* Timer count registers */
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u32 status[3];
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u32 ie[3];
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u32 preload[3]; /* Timer preload value */
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u32 preload_ctrl[3];
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u32 wdt_match_en;
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u32 wdt_match_r;
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u32 wdt_val;
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u32 wdt_sts;
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u32 icr[3];
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u32 wdt_icr;
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u32 cer; /* Timer count enable reg */
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u32 cmr;
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u32 ilr[3];
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u32 wcr;
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u32 wfar;
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u32 wsar;
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u32 cvwr[3];
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};
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#define TIMER 0 /* Use TIMER 0 */
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/* Each timer has 3 match registers */
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#define MATCH_CMP(x) ((3 * TIMER) + x)
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#define TIMER_LOAD_VAL 0xffffffff
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#define COUNT_RD_REQ 0x1
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DECLARE_GLOBAL_DATA_PTR;
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/* Using gd->tbu from timestamp and gd->tbl for lastdec */
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/*
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* For preventing risk of instability in reading counter value,
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* first set read request to register cvwr and then read same
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* register after it captures counter value.
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*/
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ulong read_timer(void)
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{
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struct panthtmr_registers *panthtimers =
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(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
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volatile int loop=100;
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ulong val;
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writel(COUNT_RD_REQ, &panthtimers->cvwr);
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while (loop--)
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val = readl(&panthtimers->cvwr);
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/*
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* This stop gcc complain and prevent loop mistake init to 0
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*/
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val = readl(&panthtimers->cvwr);
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return val;
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}
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ulong get_timer_masked(void)
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{
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ulong now = read_timer();
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if (now >= gd->tbl) {
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/* normal mode */
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gd->tbu += now - gd->tbl;
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} else {
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/* we have an overflow ... */
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gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
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}
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gd->tbl = now;
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return gd->tbu;
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}
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ulong get_timer(ulong base)
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{
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return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
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base);
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}
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void __udelay(unsigned long usec)
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{
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ulong delayticks;
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ulong endtime;
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delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
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endtime = get_timer_masked() + delayticks;
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while (get_timer_masked() < endtime)
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;
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}
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/*
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* init the Timer
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*/
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int timer_init(void)
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{
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struct panthapb_registers *apb1clkres =
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(struct panthapb_registers *) PANTHEON_APBC_BASE;
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struct panthtmr_registers *panthtimers =
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(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
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/* Enable Timer clock at 3.25 MHZ */
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writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
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/* load value into timer */
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writel(0x0, &panthtimers->clk_ctrl);
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/* Use Timer 0 Match Resiger 0 */
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writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
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/* Preload value is 0 */
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writel(0x0, &panthtimers->preload[TIMER]);
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/* Enable match comparator 0 for Timer 0 */
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writel(0x1, &panthtimers->preload_ctrl[TIMER]);
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/* Enable timer 0 */
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writel(0x1, &panthtimers->cer);
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/* init the gd->tbu and gd->tbl value */
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gd->tbl = read_timer();
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gd->tbu = 0;
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return 0;
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}
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#define MPMU_APRR_WDTR (1<<4)
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#define TMR_WFAR 0xbaba /* WDT Register First key */
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#define TMP_WSAR 0xeb10 /* WDT Register Second key */
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/*
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* This function uses internal Watchdog Timer
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* based reset mechanism.
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* Steps to write watchdog registers (protected access)
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* 1. Write key value to TMR_WFAR reg.
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* 2. Write key value to TMP_WSAR reg.
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* 3. Perform write operation.
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*/
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void reset_cpu (unsigned long ignored)
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{
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struct panthmpmu_registers *mpmu =
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(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
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struct panthtmr_registers *panthtimers =
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(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
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u32 val;
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/* negate hardware reset to the WDT after system reset */
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val = readl(&mpmu->aprr);
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val = val | MPMU_APRR_WDTR;
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writel(val, &mpmu->aprr);
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/* reset/enable WDT clock */
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writel(APBC_APBCLK, &mpmu->wdtpcr);
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/* clear previous WDT status */
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writel(TMR_WFAR, &panthtimers->wfar);
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writel(TMP_WSAR, &panthtimers->wsar);
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writel(0, &panthtimers->wdt_sts);
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/* set match counter */
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writel(TMR_WFAR, &panthtimers->wfar);
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writel(TMP_WSAR, &panthtimers->wsar);
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writel(0xf, &panthtimers->wdt_match_r);
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/* enable WDT reset */
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writel(TMR_WFAR, &panthtimers->wfar);
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writel(TMP_WSAR, &panthtimers->wsar);
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writel(0x3, &panthtimers->wdt_match_en);
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/*enable functional WDT clock */
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writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
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}
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