mirror of
https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
243 lines
8.2 KiB
C
243 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2017 Glider bvba
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*
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* Based on clk-rcar-gen2.c
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen2-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL1_DIV2,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a7792_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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/* Core Clock Outputs */
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DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
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DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
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DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
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DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
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DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
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DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
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DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
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DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
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DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
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DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
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DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
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DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
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DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
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DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
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DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
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DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
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DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
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DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
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DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
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DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
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DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
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};
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static const struct mssr_mod_clk r8a7792_mod_clks[] = {
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DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
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DEF_MOD("jpu", 106, R8A7792_CLK_M2),
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DEF_MOD("tmu1", 111, R8A7792_CLK_P),
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DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
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DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
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DEF_MOD("tmu3", 121, R8A7792_CLK_P),
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DEF_MOD("tmu2", 122, R8A7792_CLK_P),
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DEF_MOD("cmt0", 124, R8A7792_CLK_R),
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DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
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DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
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DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
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DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
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DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
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DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
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DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
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DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
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DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
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DEF_MOD("cmt1", 329, R8A7792_CLK_R),
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DEF_MOD("rwdt", 402, R8A7792_CLK_R),
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DEF_MOD("irqc", 407, R8A7792_CLK_CP),
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DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
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DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
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DEF_MOD("thermal", 522, CLK_EXTAL),
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DEF_MOD("pwm", 523, R8A7792_CLK_P),
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DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
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DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
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DEF_MOD("scif3", 718, R8A7792_CLK_P),
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DEF_MOD("scif2", 719, R8A7792_CLK_P),
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DEF_MOD("scif1", 720, R8A7792_CLK_P),
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DEF_MOD("scif0", 721, R8A7792_CLK_P),
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DEF_MOD("du1", 723, R8A7792_CLK_ZX),
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DEF_MOD("du0", 724, R8A7792_CLK_ZX),
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DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
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DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
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DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
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DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
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DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
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DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
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DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
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DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
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DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
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DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
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DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
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DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
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DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
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DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
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DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
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DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
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DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
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DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
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DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
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DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
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DEF_MOD("can1", 915, R8A7792_CLK_P),
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DEF_MOD("can0", 916, R8A7792_CLK_P),
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DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
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DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
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DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
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DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
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DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
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DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
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DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
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DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
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DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
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DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
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DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *2
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*---------------------------------------------------
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* 0 0 0 15 x200/3 x208/2 x106
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* 0 0 1 15 x200/3 x208/2 x88
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* 0 1 0 20 x150/3 x156/2 x80
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* 0 1 1 20 x150/3 x156/2 x66
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* 1 0 0 26 / 2 x230/3 x240/2 x122
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* 1 0 1 26 / 2 x230/3 x240/2 x102
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* 1 1 0 30 / 2 x200/3 x208/2 x106
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* 1 1 1 30 / 2 x200/3 x208/2 x88
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*
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* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
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* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
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(((md) & BIT(13)) >> 12) | \
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(((md) & BIT(19)) >> 19))
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static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
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{ 1, 208, 106, 200 },
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{ 1, 208, 88, 200 },
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{ 1, 156, 80, 150 },
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{ 1, 156, 66, 150 },
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{ 2, 240, 122, 230 },
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{ 2, 240, 102, 230 },
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{ 2, 208, 106, 200 },
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{ 2, 208, 88, 200 },
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};
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static const struct mstp_stop_table r8a7792_mstp_table[] = {
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{ 0x00400801, 0x400000, 0x00400801, 0x0 },
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{ 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
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{ 0x108CE100, 0x0, 0x108CE100, 0x80000 },
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{ 0x20004010, 0x4000, 0x20004010, 0x0 },
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{ 0x80000184, 0x180, 0x80000184, 0x0 },
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{ 0x44C00004, 0x0, 0x44C00004, 0x0 },
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{ 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
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{ 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
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{ 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
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{ 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
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{ 0x00001820, 0x0, 0x00001820, 0x0 },
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{ 0x00000008, 0x0, 0x00000008, 0x0 },
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};
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static const void *r8a7792_get_pll_config(const u32 cpg_mode)
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{
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return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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}
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static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
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.core_clk = r8a7792_core_clks,
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.core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
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.mod_clk = r8a7792_mod_clks,
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.mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
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.mstp_table = r8a7792_mstp_table,
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.mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
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.reset_node = "renesas,r8a7792-rst",
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.mod_clk_base = MOD_CLK_BASE,
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.clk_extal_id = CLK_EXTAL,
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.pll0_div = 2,
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.get_pll_config = r8a7792_get_pll_config,
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};
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static const struct udevice_id r8a7792_clk_ids[] = {
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{
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.compatible = "renesas,r8a7792-cpg-mssr",
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.data = (ulong)&r8a7792_cpg_mssr_info
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},
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{
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.compatible = "renesas,r8a7793-cpg-mssr",
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.data = (ulong)&r8a7792_cpg_mssr_info
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},
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{ }
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};
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U_BOOT_DRIVER(clk_r8a7792) = {
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.name = "clk_r8a7792",
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.id = UCLASS_CLK,
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.of_match = r8a7792_clk_ids,
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.priv_auto = sizeof(struct gen2_clk_priv),
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.ops = &gen2_clk_ops,
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.probe = gen2_clk_probe,
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.remove = gen2_clk_remove,
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};
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