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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
337 lines
5.0 KiB
C
337 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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/*
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* CPU test
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* Condition register istructions: mtcr, mfcr, mcrxr,
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* crand, crandc, cror, crorc, crxor,
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* crnand, crnor, creqv, mcrf
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*
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* The mtcrf/mfcr instructions is tested by loading different
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* values into the condition register (mtcrf), moving its value
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* to a general-purpose register (mfcr) and comparing this value
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* with the expected one.
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* The mcrxr instruction is tested by loading a fixed value
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* into the XER register (mtspr), moving XER value to the
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* condition register (mcrxr), moving it to a general-purpose
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* register (mfcr) and comparing the value of this register with
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* the expected one.
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* The rest of instructions is tested by loading a fixed
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* value into the condition register (mtcrf), executing each
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* instruction several times to modify all 4-bit condition
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* fields, moving the value of the conditional register to a
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* general-purpose register (mfcr) and comparing it with the
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* expected one.
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*/
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#include <post.h>
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#include "cpu_asm.h"
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#if CONFIG_POST & CONFIG_SYS_POST_CPU
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extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
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extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3);
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static ulong cpu_post_cr_table1[] =
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{
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0xaaaaaaaa,
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0x55555555,
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};
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static unsigned int cpu_post_cr_size1 = ARRAY_SIZE(cpu_post_cr_table1);
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static struct cpu_post_cr_s2 {
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ulong xer;
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ulong cr;
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} cpu_post_cr_table2[] =
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{
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{
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0xa0000000,
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1
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},
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{
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0x40000000,
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5
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},
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};
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static unsigned int cpu_post_cr_size2 = ARRAY_SIZE(cpu_post_cr_table2);
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static struct cpu_post_cr_s3 {
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ulong cr;
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ulong cs;
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ulong cd;
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ulong res;
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} cpu_post_cr_table3[] =
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{
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{
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0x01234567,
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0,
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4,
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0x01230567
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},
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{
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0x01234567,
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7,
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0,
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0x71234567
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},
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};
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static unsigned int cpu_post_cr_size3 = ARRAY_SIZE(cpu_post_cr_table3);
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static struct cpu_post_cr_s4 {
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ulong cmd;
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ulong cr;
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ulong op1;
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ulong op2;
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ulong op3;
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ulong res;
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} cpu_post_cr_table4[] =
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{
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{
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OP_CRAND,
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0x0000ffff,
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0,
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16,
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0,
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0x0000ffff
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},
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{
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OP_CRAND,
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0x0000ffff,
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16,
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17,
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0,
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0x8000ffff
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},
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{
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OP_CRANDC,
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0x0000ffff,
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0,
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16,
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0,
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0x0000ffff
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},
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{
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OP_CRANDC,
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0x0000ffff,
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16,
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0,
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0,
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0x8000ffff
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},
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{
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OP_CROR,
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0x0000ffff,
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0,
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16,
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0,
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0x8000ffff
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},
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{
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OP_CROR,
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0x0000ffff,
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0,
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1,
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0,
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0x0000ffff
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},
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{
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OP_CRORC,
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0x0000ffff,
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0,
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16,
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0,
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0x0000ffff
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},
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{
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OP_CRORC,
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0x0000ffff,
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0,
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0,
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0,
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0x8000ffff
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},
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{
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OP_CRXOR,
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0x0000ffff,
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0,
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0,
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0,
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0x0000ffff
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},
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{
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OP_CRXOR,
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0x0000ffff,
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0,
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16,
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0,
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0x8000ffff
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},
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{
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OP_CRNAND,
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0x0000ffff,
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0,
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16,
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0,
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0x8000ffff
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},
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{
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OP_CRNAND,
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0x0000ffff,
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16,
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17,
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0,
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0x0000ffff
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},
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{
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OP_CRNOR,
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0x0000ffff,
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0,
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16,
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0,
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0x0000ffff
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},
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{
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OP_CRNOR,
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0x0000ffff,
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0,
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1,
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0,
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0x8000ffff
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},
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{
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OP_CREQV,
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0x0000ffff,
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0,
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0,
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0,
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0x8000ffff
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},
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{
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OP_CREQV,
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0x0000ffff,
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0,
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16,
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0,
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0x0000ffff
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},
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};
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static unsigned int cpu_post_cr_size4 = ARRAY_SIZE(cpu_post_cr_table4);
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int cpu_post_test_cr (void)
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{
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int ret = 0;
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unsigned int i;
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unsigned long cr_sav;
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int flag = disable_interrupts();
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asm ( "mfcr %0" : "=r" (cr_sav) : );
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for (i = 0; i < cpu_post_cr_size1 && ret == 0; i++)
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{
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ulong cr = cpu_post_cr_table1[i];
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ulong res;
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unsigned long code[] =
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{
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ASM_MTCR(3),
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ASM_MFCR(3),
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ASM_BLR,
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};
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cpu_post_exec_11 (code, &res, cr);
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ret = res == cr ? 0 : -1;
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if (ret != 0)
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{
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post_log ("Error at cr1 test %d !\n", i);
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}
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}
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for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++)
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{
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struct cpu_post_cr_s2 *test = cpu_post_cr_table2 + i;
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ulong res;
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ulong xer;
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unsigned long code[] =
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{
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ASM_MTXER(3),
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ASM_MCRXR(test->cr),
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ASM_MFCR(3),
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ASM_MFXER(4),
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ASM_BLR,
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};
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cpu_post_exec_21x (code, &res, &xer, test->xer);
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ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ?
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0 : -1;
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if (ret != 0)
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{
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post_log ("Error at cr2 test %d !\n", i);
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}
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}
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for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++)
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{
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struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i;
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ulong res;
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unsigned long code[] =
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{
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ASM_MTCR(3),
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ASM_MCRF(test->cd, test->cs),
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ASM_MFCR(3),
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ASM_BLR,
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};
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cpu_post_exec_11 (code, &res, test->cr);
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ret = res == test->res ? 0 : -1;
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if (ret != 0)
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{
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post_log ("Error at cr3 test %d !\n", i);
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}
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}
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for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++)
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{
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struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i;
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ulong res;
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unsigned long code[] =
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{
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ASM_MTCR(3),
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ASM_12F(test->cmd, test->op3, test->op1, test->op2),
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ASM_MFCR(3),
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ASM_BLR,
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};
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cpu_post_exec_11 (code, &res, test->cr);
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ret = res == test->res ? 0 : -1;
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if (ret != 0)
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{
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post_log ("Error at cr4 test %d !\n", i);
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}
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}
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asm ( "mtcr %0" : : "r" (cr_sav));
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if (flag)
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enable_interrupts();
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return ret;
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}
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#endif
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